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參數(shù)資料
| 型號： | P83CE560 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 26/84頁 |
| 文件大?。?/td> | 441K |
| 代理商： | P83CE560 |
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1997 Aug 01
26
Philips Semiconductors
Product specification
8-bit microcontroller
P8xCE560
12.1.1
T
IMER
/C
OUNTER
M
ODE
C
ONTROL
R
EGISTER
(TMOD)
Table 26
Timer/Counter Mode Control Register (address 89H)
Table 27
Description of TMOD bits for Timer 1 and Timer 0
Timer 0: bit TMOD.0 to TMOD.3; Timer 1: bit TMOD.4 to TMOD.7; n = 0, 1.
Table 28
Timer 0, Timer 1 mode select
12.1.2
T
IMER
/C
OUNTER
C
ONTROL
R
EGISTER
(TCON)
Table 29
Timer/Counter Control Register (address 88H)
Table 30
Description of TCON bits
7
6
5
4
3
2
1
0
GATE
C/T
M1
M0
GATE
C/T
M1
M0
BIT
SYMBOL
DESCRIPTION
7 and 3
GATE
Gating control
. When set Timer/counter ‘n’ is enabled only while INTn pin is HIGH and
control bit TRn (TR1 or TR0) is set. When cleared Timer ‘n’ is enabled whenever TRn
control bit is set.
Timer or Counter Selector
. Cleared for Timer operation; input from internal system
clock. Set for Counter operation; input from pin Tn (T1 or T0).
Timer 0, Timer 1 mode select
; see Table 28.
6 and 2
C/T
5 and 1
4 and 0
M1
M0
M1
M0
OPERATING
0
0
1
0
1
0
Timer TL0/TL1 serves as 5-bit prescaler.
16-bit Timer/Counter TH0/TH1 and TL0/TL1 are cascaded; there is no prescaler.
8-bit auto-reload Timer/Counter TH0/TH1 holds a value which is to be reloaded into
TL0/TL1 each time it overflows.
Timer 0: TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
Timer 1: Timer/Counter 1 stopped.
1
1
1
1
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
BIT
SYMBOL
DESCRIPTION
7 and 5
TF1 and TF0
Timer 1 and Timer 0 overflow flag
. Set by hardware on Timer/Counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
TR1 and TR0
Timer 1 and Timer 0 run control bit
. Set/cleared by software to turn Timer/Counter
on/off.
IE1 and IE0
Interrupt 1 and Interrupt 0 edge flag
. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
IT1 and IT0
Interrupt 1 and Interrupt 0 type control bit
. Set/cleared by software to specify falling
edge/low level triggered external interrupts.
6 and 4
3 and 1
2 and 0
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