參數(shù)資料
型號(hào)： MPC8569VTANKGB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783
文件頁數(shù)： 104/126頁
文件大?。?/td> 2847K
代理商： MPC8569VTANKGB
High-Speed SerDes Interfaces (HSSI)
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
79
signal trace curve in a differential waveform. The voltage represented in the differential waveform
is not referenced to ground. See Figure 43 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each conductor of
a balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out =(VSD_TX +VSD_TX) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
complimentary output voltages within a differential pair. In a system, the common mode voltage
may often differ from one component’s output to the other’s input. It may be different between the
receiver input and driver output circuits within the same component. It is also referred to as the DC
offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (VOD) has
the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV.
In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV.
The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.9.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes.The SerDes reference clock inputs are SD_REF_CLK and SD_REF_CLK for PCI Express, Serial RapidIO, and
SGMII interface, respectively.
The following sections describe the SerDes reference clock requirements and provide application information.
2.9.2.1
SerDes Spread Spectrum Clock Source Recommendations
SD_REF_CLK/SD_REF_CLK are designed to work with spread spectrum clock for PCI Express protocol only with the
spreading specification defined in Table 46. When using spread spectrum clocking for PCI Express, both ends of the link
partners should use the same reference clock. For best results, a source without significant unintended modulation must be used.
The spread spectrum clocking cannot be used if the same SerDes reference clock is shared with other non-spread spectrum
supported protocols. For example, if the spread spectrum clocking is desired on a SerDes reference clock for PCI Express and
the same reference clock is used for any other protocol such as SGMII/SRIO due to the SerDes lane usage mapping option,
spread spectrum clocking cannot be used at all.
2.9.2.2
SerDes Reference Clock Receiver Characteristics
The following figure shows a receiver reference diagram of the SerDes reference clocks.
Table 46. SerDes Spread Spectrum Clock Source Recommendations
At recommended operating conditions. See Table 3.
Parameter
Min
Max
Unit
Notes
Frequency modulation
30
33
kHz
—
Frequency spread
+0
–0.5
%
1
Note:
1. Only down spreading is allowed.
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