參數(shù)資料
    型號(hào): NM24C16UN
    廠(chǎng)商: FAIRCHILD SEMICONDUCTOR CORP
    元件分類(lèi): PROM
    英文描述: IC-16K-BIT SERIAL EEPROM
    中文描述: 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8
    封裝: PLASTIC, DIP-8
    文件頁(yè)數(shù): 12/14頁(yè)
    文件大小: 102K
    代理商: NM24C16UN
    12
    www.fairchildsemi.com
    NM24C16/17 Rev. G
    N
    S
    T
    O
    P
    A
    C
    K
    NO
    A
    C
    K
    SLAVE
    ADDRESS
    A
    C
    K
    A
    C
    K
    S
    T
    A
    R
    T
    S
    T
    A
    R
    T
    WORD
    ADDRESS
    SLAVE
    ADDRESS
    Bus Activity:
    Master
    SDA Line
    Bus Activity:
    EEPROM
    DATA n
    S
    T
    O
    P
    A
    C
    K
    Bus Activity:
    Master
    SDA Line
    Bus Activity:
    EEPROM
    A
    C
    K
    DATA n + x
    A
    C
    K
    DATA n + 2
    DATA n +1
    DATA n +1
    A
    C
    K
    NO
    A
    C
    K
    Slave
    Address
    DS500072-17
    DS500072-18
    Read Operations
    Read operations are initiated in the same manner as write
    operations, with the exception that the R/W bit of the slave
    address is set to a one. There are three basic read operations:
    current address read, random read, and sequential read.
    Current Address Read
    Internally the NM24C16/17 contains an address counter that
    maintains the address of the last byte accessed, incremented by
    one. Therefore, if the last access (either a read or write) was to
    address n, the next read operation would access data from
    address n + 1. Upon receipt of the slave address with R/W set to
    one, the NM24C16/17 issues an acknowledge and transmits the
    eight bit byte. The master will not acknowledge the transfer but
    does generate a stop condition, and therefore the NM24C16/17
    discontinues transmission. Refer to Figure 6 or the sequence of
    address, acknowledge and data transfer.
    Random Read
    Random read operations allow the master to access any memory
    location in a random manner. Prior to issuing the slave address
    with the R/W bit set to one, the master must first perform a
    dummy
    write operation. The master issues the start condition,
    slave address with the R/W bit set to zero and then the byte
    address it is to read. After the byte address acknowledge, the
    master immediately issues another start condition and the slave
    address with the R/W bit set to one. This will be followed by an
    acknowledge from the NM24C16/17 and then by the eight bit byte.
    The master will not acknowledge the transfer but does generate
    the stop condition, and therefore the NM24C16/17 discontinues
    transmission. Refer to Figure 7 for the address, acknowledge and
    data transfer sequence.
    Sequential Read
    Sequential reads can be initiated as either a current address read
    or random access read. The first word is transmitted in the same
    manner as the other read modes; however, the master now
    responds with an acknowledge, indicating it requires additional
    data. The NM24C16/17 continues to output data for each ac-
    knowledge received. The read operation is terminated by the
    master not responding with an acknowledge or by generating a
    stop condition.
    The data output is sequential, with the data from address n
    followed by the data from n + 1. The address counter for read
    operations increments all word address bits, allowing the entire
    memory contents to be serially read during one operation. After
    the entire memory has been read, the counter "rolls over" to the
    beginning of the memory. NM24C16/17 continues to output data
    for each acknowledge received. Refer to Figure 8for the address,
    acknowledge, and data transfer sequence.
    Current Address Read (Figure 6)
    S
    T
    O
    P
    DATA
    A
    C
    K
    NO
    A
    C
    K
    S
    T
    A
    R
    T
    SLAVE
    ADDRESS
    Bus Activity:
    Master
    SDA Line
    Bus Activity:
    EEPROM
    1 0 1 0 1
    DS500072-16
    Random Read (Figure 7)
    Sequential Read (Figure 8)
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