參數(shù)資料
型號(hào): NDS355N
廠(chǎng)商: FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi): 小信號(hào)晶體管
英文描述: N-Channel Logic Level Enhancement Mode Field Effect Transistor(1.6A,30V,0.125Ω)(N溝道邏輯增強(qiáng)型MOS場(chǎng)效應(yīng)管(漏電流1.6A, 漏源電壓30V,導(dǎo)通電阻0.125Ω))
中文描述: 1600 mA, 30 V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET
封裝: SUPERSOT-3
文件頁(yè)數(shù): 3/6頁(yè)
文件大?。?/td> 74K
代理商: NDS355N
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Maximum Continuous Source Current
0.6
A
Maximum Pulse Source Current
(Note 2)
6
A
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.6 A
0.8
1.2
V
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
P
D
(
t
) =
T
J
T
A
R
θ
J A
(
t
)
=
T
J
T
A
R
θ
J C
+
R
θ
CA
(
t
)
=
I
D
2
(
t
R
DS
(
ON
)
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250
o
C/W when mounted on a 0.02 in
2
pad of 2oz cpper.
b. 270
o
C/W when mounted on a 0.001 in
2
pad of 2oz cpper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%.
NDS355N Rev. D1
1a
1b
相關(guān)PDF資料
PDF描述
NDS356AP P-Channel Logic Level Enhancement Mode Field Effect Transistor(-1.1A,-30V,0.3Ω)(P溝道邏輯增強(qiáng)型MOS場(chǎng)效應(yīng)管(漏電流-1.1A, 漏源電壓-30V,導(dǎo)通電阻0.3Ω))
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NDS355N 制造商:Fairchild Semiconductor Corporation 功能描述:MOSFET N SOT-23
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