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參數(shù)資料
| 型號(hào)： | MTB50P03HDL |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET LOGIC LEVEL 50 AMPERES 30 VOLTS |
| 中文描述： | 50 A, 30 V, 0.03 ohm, P-CHANNEL, Si, POWER, MOSFET |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 182K |
| 代理商： | MTB50P03HDL |
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25
°
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250
μ
Adc)
Temperature Coefficient (Positive)
(Cpk
≥
2.0) (3)
V(BR)DSS
30
—
—
26
—
—
Vdc
mV/
°
C
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125
°
C)
IDSS
—
—
—
—
1.0
10
μ
Adc
Gate–Body Leakage Current
(VGS =
±
15 Vdc, VDS = 0 Vdc)
IGSS
—
—
100
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
μ
Adc)
Threshold Temperature Coefficient (Negative)
(Cpk
≥
3.0) (3)
VGS(th)
1.0
—
1.5
4.0
2.0
—
Vdc
mV/
°
C
Static Drain–Source On–Resistance
(VGS = 5.0 Vdc, ID = 25 Adc)
(Cpk
≥
3.0) (3)
RDS(on)
—
20.9
25
mOhm
Drain–Source On–Voltage (VGS = 5.0 Vdc)
(ID = 50 Adc)
(ID = 25 Adc, TJ =125
°
C)
VDS(on)
—
—
0.83
—
1.5
1.3
Vdc
Forward Transconductance
(VDS = 5.0 Vdc, ID = 25 Adc)
gFS
15
20
—
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
25 Vdc V
Ciss
—
3500
4900
pF
Output Capacitance
Coss
Crss
—
1550
2170
Transfer Capacitance
—
550
770
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
(VDD= 15 Vdc, ID = 50 Adc,
VGS= 5 0 Vdc
VGS = 5.0 Vdc,
RG = 2.3
td(on)
tr
—
22
30
ns
Rise Time
—
340
466
Turn–Off Delay Time
td(off)
tf
QT
Q1
Q2
Q3
—
90
117
Fall Time
)
—
218
300
Gate Charge
(See Figure 8)
(VDS = 24 Vdc,D
(DS
VGS = 5.0 Vdc)
—
74
100
nC
—
13.6
—
,
—
44.8
—
—
35
—
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 50 Adc, VGS = 0 Vdc)
(IS = 50 Adc, VGS = 0 Vdc, TJ = 125
°
C)
VSD
—
—
2.39
1.84
3.0
—
Vdc
Reverse Recovery Time
(See Figure 15)
(IS = 50 Adc, VGS
(S
dIS/dt = 100 A/
μ
s)
trr
ta
—
106
—
ns
—
58
—
,
tb
—
48
—
Reverse Recovery Stored Charge
QRR
—
0.246
—
μ
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
″
from package to center of die)
LD
—
3.5
—
nH
Internal Source Inductance
(Measured from the source lead 0.25
″
from package to source bond pad)
LS
—
7.5
—
nH
(1) Pulse Test: Pulse Width
≤
300
μ
s, Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk =
3 x SIGMA
Max limit – Typ
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