參數(shù)資料
型號： MT57W4MH9CF-6
元件分類： SRAM
英文描述： 4M X 9 DDR SRAM, 0.5 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁數(shù)： 1/29頁
文件大?。?/td> 344K
代理商： MT57W4MH9CF-6
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
36Mb: 1.8V VDD, HSTL, QDRB2 SRAM
2003 Micron Technology, Inc.
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
1
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, DDR SIO SRAM
ADVANCE
36Mb DDR SIO SRAM
2-WORD BURST
MT57W4MH8C
MT57W4MH9C
MT57W2MH18C
MT57W1MH36C
Features
DLL circuitry for accurate output data placement
Separate independent read and write data ports
DDR READ or WRITE operation initiated each cycle
Fast clock to valid data times
Full data coherency, providing most current data
Two-tick burst counter for low DDR transaction size
Double data rate operation on read and write ports
Two input clocks (K and K#) for precise DDR timing at
clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
Optional-use echo clocks (CQ and CQ#) for flexible
receive data synchronization
Single address bus
Simple control logic for easy depth expansion
Internally self-timed, registered writes
Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.5V to VDD
(±0.1V) HSTL
Clock-stop capability with s restart
15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package
User-programmable impedance output
JTAG boundary scan
General Description
The Micron DDR separate I/O, synchronous, pipe-
lined burst SRAM employs high-speed, low-power
CMOS designs using an advanced 6T CMOS process.
The DDR architecture consists of two separate DDR
(double data rate) ports to access the memory array.
The read port has dedicated data outputs to support
READ operations. The write port has dedicated data
inputs to support WRITE operations. This architecture
eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on the rising edge of the K input clock. Each address
location is associated with two words that burst
sequentially into or out of the device. Bus turnaround
cycles are eliminated and a new data transaction can
be requested each clock cycle, permitting higher
request rates than DDR SRAMs without separated
input and output buses.
Options
Marking1
NOTE:
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
Clock Cycle Timing
3ns (333 MHz)
-3
3.3ns (300 MHz)
-3.3
4ns (250 MHz)
-4
5ns (200 MHz)
-5
6ns (167 MHz)
-6
7.5ns (133 MHz)
-7.5
Configurations
4 Meg x 8
MT57W4MH8C
4 Meg x 9
MT57W4MH9C
1 Meg x 18
MT57W2MH18C
1 Meg x 36
MT57W1MH36C
Package
165-ball, 15mm x 17mm FBGA
F
Table 1:
Valid Part Numbers
PART NUMBER
DESCRIPTION
MT57W4MH8CF-xx
4 Meg x 8, DDR SIOb2 FBGA
MT57W4MH9CF-xx
4 Meg x 9, DDR SIOb2 FBGA
MT57W2MH18CF-xx
2 Meg x 18, DDR SIOb2 FBGA
MT57W1MH36CF-xx
1Meg x 36, DDR SIOb2 FBGA
Figure 1: 165-Ball FBGA
相關PDF資料
PDF描述
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