參數(shù)資料
型號(hào)： MSC7116VF1000
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 266 MHz, OTHER DSP, PBGA400
封裝： 17 X 17 MM, MAPBGA-400
文件頁(yè)數(shù)： 16/60頁(yè)
文件大?。?/td> 1566K
代理商： MSC7116VF1000
Electrical Characteristics
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
23
2.5.2.3
Multiplication Factor Range
The multiplier block output frequency ranges depend on the divided input clock frequency as shown in Table 10.
2.5.2.4
Allowed Core Clock Frequency Range
The frequency delivered to the core, extended core, and peripherals depends on the value of the CLKCTRL[RNG] bit as shown
This bit along with the CKSEL determines the frequency range of the core clock.
2.5.2.5
Core Clock Frequency Range When Using DDR Memory
The core clock can also be limited by the frequency range of the DDR devices in the system. Table 13 summarizes this
restriction.
Table 10. PLLMLTF Ranges
Multiplier Block (Loop) Output Range
Minimum PLLMLTF Value
Maximum PLLMLTF Value
266
≤ [Divided Input Clock × (PLLMLTF + 1)] ≤ 532 MHz
266/Divided Input Clock
532/Divided Input Clock
Note:
This table results from the allowed range for FLoop. The minimum and maximum multiplication factors are dependent on the
frequency of the Divided Input Clock.
Table 11. Fvco Frequency Ranges
CLKCTRL[RNG] Value
Allowed Range of Fvco
1
266
≤ Fvco ≤ 532 MHz
0
133
≤ Fvco ≤ 266 MHz
Note:
This table results from the allowed range for Fvco, which is FLoop modified by CLKCTRL[RNG].
Table 12. Resulting Ranges Permitted for the Core Clock
CLKCTRL[CKSEL]
CLKCTRL[RNG]
Resulting
Division
Factor
Allowed Range
of Core Clock
Comments
11
1
Reserved
11
0
2
133
≤ core clock ≤ 266 MHz
Limited by range of PLL
01
1
2
133
≤ core clock ≤ 266 MHz
Limited by range of PLL
01
0
4
66.5
≤ core clock ≤ 133 MHz
Limited by range of PLL
Note:
This table results from the allowed range for FOUT, which depends on clock selected via CLKCTRL[CKSEL].
Table 13. Core Clock Ranges When Using DDR
DDR Type
Allowed Frequency
Range for DDR CK
Corresponding Range
for the Core Clock
Comments
DDR 200 (PC-1600)
83–100 MHz
166
≤ core clock ≤ 200 MHz
Core limited to 2
× maximum DDR frequency
DDR 266 (PC-2100)
DDR 333 (PC-2600)
83–133 MHz
166
≤ core clock ≤ 266 MHz
Core limited to 2
× maximum DDR frequency
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC7116VF1000,
MSC7116VM1000,
MSC711XADS
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