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參數(shù)資料
| 型號： | MPC7400RX350LK |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | CERAMIC, BGA-360 |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 504K |
| 代理商： | MPC7400RX350LK |
Power Management
MPC7400 microprocessors feature a low-power 1.8-volt design with three power-saving user-programmable modes —
nap, doze (with bus snoop) and sleep— which progressively reduce the power drawn by the processor. The MPC7400
also provides a thermal assist unit and instruction cache throttling for software-controllable thermal management.
Cache and MMU Support
The MPC7400 microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches. Both caches
feature cache locking and are eight-way set-associative. The MPC7400 microprocessor’s dedicated L2 cache interface
with on-chip L2 tags features a very fast (up to core speed, 1:1) interface to memory, instruction-only or data-only
modes, and parity checking on both L2 address and data.
MPC7400 microprocessors contain separate memory management units (MMUs) for instructions and data, supporting
4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical memory. They also offer four instruction block
address translation (iBAT) and four data block address translation (dBAT) registers.
MPX Bus Interface
MPC7400 microprocessors support the MPX bus architecture with a 64-bit data bus and a 32-bit address bus. Support
is included for burst, split and pipelined transactions, data streaming, out-of-order transactions, and data intervention (in
SMP systems). The interface provides snooping for
data cache coherency. The MPC7400 implements
MERSI coherency protocol for multiprocessing in
hardware, allowing access to system memory for
additional caching bus masters, such as DMA
devices.
Example Applications
I
Networking and telecommunications
infrastructure
I
High-performance computing (scientific,
medical, etc.)
I
Desktop and portable computing
Contact Information
Motorola offers user’s manuals, application notes,
sample code and full local support for the PowerPC
product line. For more information, visit:
http://motorola.com/PowerPC/ and
http://motorola.com/AltiVec/
For all other inquiries about Motorola products,
please contact the Motorola Customer Response
Center at: 1-800-521-6274 or
http://motorola.com/semiconductors
Motorola PowerPC 7xxx Part Number Key
7xxx Series Device
(7400)
XPC
7400
RX
400
L
K
Product Code
PPC Sample
XPC XC qualified
MPC Qualified
Frequency
3 digits
Spec Definition
L1.8V, 105
°C
P
2.15V, 65
°C
Revision
Package
RX CBGA w/o Lid
CPU Speeds – Internal
CPU Bus Dividers
Bus Protocol
Instructions per Clock
L2 Cache
Typical/Maximum
Power Dissipation
Die Size
Package
Process
Voltage
SPECint95 (estimated)
SPECfp95 (estimated)
Other Performance
Execution Units
L1 Cache
Core-to-L2 Frequency
350, 400, 450, and 500 MHz
64-bit
Bus Interface
MPX/60x
3 (2 + Branch)
512 Kbyte,
1 Mbyte, or 2 Mbyte
32-Kbyte instruction
32-Kbyte data
5.0W/11.5W @ 400 MHz
83 mm2
1:1, 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1
360 CBGA
0.18
5LM CMOS
1.8V internal, 1.8/2.5/3.3V I/O
21.4 @ 450 MHz
20.4 @ 450 MHz
825 MIPS @ 450 MHz
Integer(2), Floating-Point, Vector,
Branch, Load/Store, System
x3, x3.5, x4, x4.5, x5, x5.5,
x6, x6.5, x7, x7.5, x8, x9
MPC7400
350-500 MHz
Motorola MPC7400 Processor Summary
2000 Motorola, Inc. All rights reserved. Printed in the U.S.A. Motorola and the Motorola logo are registered trademarks and DigitalDNA, the DigitalDNA logo and AltiVec are
trademarks of Motorola, Inc. PowerPC, the PowerPC logo, PowerPC 603e, PowerPC 740, and PowerPC 750 are trademarks of International Business Machines Corporation and
used under license therefrom. All other trademarks are the property of their respective owners.
1ATX45602-1 Printed in USA 5/00 Hibbert LITRISC
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