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參數(shù)資料
| 型號： | MN195007 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 24.576 MHz, OTHER DSP, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 30/30頁 |
| 文件大?。?/td> | 280K |
| 代理商： | MN195007 |
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MN195007 Hardware Specifications
Panasonic Communications Co., Ltd.
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9 -
2.3 Pin Definitions
2.3.1 Unique Pin
a) XI, XO
Connect a 24.576 MHz crystal resonator.
Use a crystal resonator only with its frequency deviations not exceeding ±50 × 10-6 (with
aging and temperature changes included).
When using a crystal oscillator, apply a signal to XI, leaving XO open.
Duty ratio:
40% to 60%
Frequency deviation:
Not exceeding ±50 × 10-6 (with aging and
temperature changes included)
b) CLKOUT
Buffered output of the signal input from a quartz resonator or quartz oscillator.
Use CLKOUT as an AFE clock.
Output clock signal during reset.
c) LON
Test pin.
Set “High” set on this pin during normal operations.
d) CKON
Oscillation operation control and internal PLL control pin when a quartz resonator
oscillator is used.
“High” starts oscillation, and “Low” stops oscillation.
Keep “High” set on this pin during normal operations.
e) MINTEST, TEST1, TEST2
Test pins
Keep “Low” set on these pins during normal operations.
f) Mode [1:0]
Operation mode select pins
Mode [1]
Mode [2]
Operation Mode
0
DSP Mode
0
1
Parallel i/f Mode
1
0
Serial i/f Mode
1
Not used ( inhibit )
[ Table 4 ] Operation Mode List
g) NRESET
Reset pin
“Low” on NRESET enables a reset; “High” cancels the reset.
On a reset, the internal clock shuts down, saving the current drain.
A reset takes effect in a minimum “Low” period of 100 ns while the power input and the
CLKON pin are stable. Internal circuitry stabilizes 50 ms after the reset is canceled,
getting the modem operation started.
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