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參數(shù)資料
| 型號： | MN195007 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 24.576 MHz, OTHER DSP, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 280K |
| 代理商： | MN195007 |
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MN195007 Hardware Specifications
Panasonic Communications Co., Ltd.
-
11 -
k) DP
Dialing pulse Output pin
The default is a high
(i.e.) When dialing “3”
ON Huck Condition
OFF Huck Condition
Reset / Idol
During Plus Calling
PB Waiting
* Please refer “MMD-5005 Modem Type 3 interface D-Mode Specifications” for more
details
l) Ring
Ringing pulse input pin for ring detection
Apply a ringing signal at the +3.3V logic level.
Calculates the period between rising or falling edges of an input pulse.
* Please refer “MMD-5005 Modem Type 3 interface D-Mode Specifications” for more
details
m) AFERST
AFE reset signal.
Output “Low” signal during Reset ( NRESET signal is “Low” )
n) VDD3
+3.3V power pin
Supply +3.3V from an external source.
o) VDDREG
Internal regulator (+1.8V output) power pin
Supply +3.3V.
p) VREGOUT1, REGOUT2
Internal regulator voltage (+1.8V） output pins
Have a capacitor rated at 4.7F or higher inserted between these pins and VSS to
stabilize the regulator.
Wire this pin to VDD2.
q) VDD2
+1.8V power input pin. (Power supplied to internal logic operation from +1.8V)
Wire VDD2 to REGOUT and have a capacitor inserted between VDD2 and VSS.
r) VSS
GND pin.
There is no distinction between +3.3V power and +1.8V power VSSs.
s) AVDD
PLL block power pin
Supply +3.3V. There is no need to distinguish AVDD from VDD3 and VDDREG.
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