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參數(shù)資料
| 型號： | MN195007 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-BIT, 24.576 MHz, OTHER DSP, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 16/30頁 |
| 文件大?。?/td> | 280K |
| 代理商： | MN195007 |
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MN195007 Hardware Specifications
Panasonic Communications Co., Ltd.
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23 -
6. Function Explanation in each Mode
6.1 DSP Mode
6.1.1 Dual Port Memory Brock
Physical interface between Host CPU, is used 2Kbytes dual port memory ( DPRAM ) and
both 16 and 8 bit access is available.
6.1.1.1 Access Timing
Assess timing is mentioned in [ Figure 6 ] and [ Figure 7 ].
It is the common timing to access DPRAM and Type 3 interface register ( Refer to “6.1.2
Type 3 Interface Register” )
Normal timing
If NDPWR is delayed
after NUB, NLB
Item
Symb
ol
Min
Max
Min
Max
Unit
DPA set-up
tSA
30
40
ns
DPA Hold
tHA
0
-10
ns
DPD Set-up
tSD
30
40
ns
DPD Hold
tHD
0
-10
ns
NDPCS Set-up
tSC
30
40
ns
NDPCS Hold
tHC
0
-10
ns
NUB, NLB Set-up
tSB
30
40
ns
NUB, NLB Hold
tHB
0
-10
ns
NDPCS Negation Period
tNC
20
ns
NDPWR Hold during NDPCS Negation
tHWC
3
ns
NDPRD Hold during NDPCS Negation
tHRC
3
ns
NDPWR Pulse Width
tWW
40
ns
NDPWR Negation Period
tNW
20
ns
NDPCS Hold during NDPWR Negation
tHCW
3
ns
NDPRD Pulse Width
tWR
100
ns
NDPCS Hold during NDPRD Negation
tHCW
3
ns
NDPRD Negation Period
tNR
20
ns
NDPRD Access Time
tAR
100
ns
DPA Access Time
tAA
100
ns
NDPCS Access Time
tAC
100
ns
NUB, NLB Access Time
tAB
100
ns
DPD Output Hold Time
tHRD
5
ns
[ Table 15 ] DPRAM Access Time
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