參數(shù)資料
型號: ML610Q407-NNNTBZ03A
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14MM, 0.50 PITCH, PLASTIC, TQFP-100
文件頁數(shù): 57/62頁
文件大?。?/td> 1994K
代理商: ML610Q407-NNNTBZ03A
REVISION HISTORY
Rev.
Date
Description
Page
Summary
M32C/80 Group Datasheet
A-2
Electrical Characteristics
30-
This capter added
All pages
Package code chnaged: 100P6Q-A to PLQP0100KB-A and 100P6S-A to PRQP0100JB-A
Overview
1
Note that the M32C/80 Group is ROMless device added
2
Table 1.1 M32C/80 Group Performance Item "HDLC Data Processing" changed
to "Intelligent I/O Communication Function"; item "Flash Memory" deleted
3
Figure 1.1 M32C/80 Group Block Diagram Notes 1 and 2 added
9
Table 1.4 Pin Description Supply voltage for analog power supply input modi-
______
fied "-" to "VCC1"; description for CNVSS changed; supply voltage for INT inter-
rupt input modified; note for I/O ports added
Memory
15
Figure 3.1 Memory Map Disgram changed; note added
Special Function Registers (SFRs)
16
Note 2 deleted
17
Values after RESET in the RMAD6 and RMAD7 registers modified
19
Value after RESET in the RLVL register modified
20
Value after RESET in the G0RB register modified
21
Values after RESET in the G0EMR, G0ERC, and G0IRF registers modified
26
Value after RESET in the TCSPR register modified; note 1 added
27, 28
Register names, symbols, and value after RESET of addresses 039216 and
03AC16 deleted
28
Value after RESET in the PSC register modified
Electrical Characteristics
30-
Ports P11 to P15 deleted
32
Table 5.2 Recpmmended Operating Conditions f(BCLK) standard added
33
Table 5.3 Electrical Characteristics Max. standard for ICC modified
34
Table 5.4 A/D Conversion Characteristics AN00 to AN07 deleted from "INL" row
35
Table 5.7 Memory Expansion Mode and Microprocessor Mode Expressions
on note 1 corrected
41
Figure 5.2 VCC1=VCC2=5V Timing Diagram (1) Expression for tcyc added; note 3
corrected
42
Figure 5.3 VCC1=VCC2=5V Timing Diagram (2) Expression for tcyc added; notes
1 and 2 corrected
46
Table 5.22 A/D Conversion Characteristics Min. standard for VREF modified
47
Table 5.25 Memory Expansion Mode and Microprocessor Mode Expres-
sions on note 1 corrected
52
Figure 5.6 VCC1=VCC2=3.3V Timing Diagram (1) Expression for tcyc added; note
3 corrected
1.10
Nov., 05
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