參數(shù)資料
型號: MK2715-01STR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 17.7345 MHz, VIDEO CLOCK GENERATOR, PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 3/4頁
文件大?。?/td> 26K
代理商: MK2715-01STR
MK2715
NTSC/PAL Clock Source
MDS2715B
3
Revision 8157
Printed 9/19/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
250
°C
Storage Temperature
-65
150
°C
DC CHARACTERISTICS
Operating Voltage, VDD
4.5
5
5.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage
IOH=-4mA
VDD-0.4
V
Output High Voltage
IOH=-25mA
2.4
V
Output Low Voltage
IOL=25mA
0.4
V
Operating Supply Current, IDD
No Load
22
mA
Standby Supply Current, IDDPD
No Load, PD=0V
20
A
Short Circuit Current
Each output
±100
mA
Input Capacitance
S0, S1 pins
7
pF
Actual mean frequency error versus target, note 2
Ex 14.328, 3.582 MHz
0
ppm
Actual mean frequency error versus target
14.328, 3.582 MHz
14
ppm
AC CHARACTERISTICS
Input Frequency
13.5
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
Time above 1.4V
45
49 to 51
55
%
Power down Time, PD taken low to clocks off
1
s
Power up Time, PD taken high to clocks stable
10
ms
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Provided the crystal is properly tuned, or an accurate 13.5000 MHz input clock is used.
Electrical Specifications (at 5.0V unless otherwise noted)
External Components/Crystal Selection
The MK2715 requires a minimum number of external components for proper operation. For a crystal input,
a parallel resonant 13.5000 MHz crystal is recommended, with frequency tolerance of 50ppm or better.
Crystal capacitors should be connected from each of the pins X1 and X2 to Ground. The value (in pF) of
these crystal caps should be = (CL-8)*2, where CL is the crystal load capacitance in pF. For a clock input,
connect to X1 and leave X2 unconnected. Multiple VDD and GND pins should be connected together,
and a decoupling capacitor of 0.1F must be connected between them very close to the chip. A 33
terminating resistors can be used on clock outputs with traces longer than 1 inch.
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