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參數(shù)資料
| 型號： | MK2049-02 |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 87K |
| 代理商： | MK2049-02 |
MK2049-02
Communications Clock PLL
MDS2049-02
4
Revision 7309
Printed 7/30/99
MicroClock Division of ICS 525 Race Street San Jose CA 95126 (408)295-9800tel(408)295-9818fax
ICRO
CLOCK
ADVANCE
ADVANCE INFORMATION
INFORMATION
Operating Modes (continued)
Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a
wider range of input clocks. The input jitter is attenuated, and the outputs on CLK1 and CLK2 also
provide the option of getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be
used to remove the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs.
Input And Output Synchronization
As shown in the tables on page 3, the MK2049-02 offers a Zero Delay feature in most selections. In these
selections, there is an internal feedback path between ICLK and the CLK2 output clock. This provides a
fixed phase relationship between the input and output, a requirement in many communications systems.
As shown in the diagram below, when using one of the Zero Delay selections, the rising edge of ICLK will
be aligned with the rising edge of CLK2. However, the CLK1 edge in these cases will be either rising or
falling. (8 kHz is used in this illustration, but the same is true for the Zero Delay selections with MHz
inputs.)
ICLK (8 kHz)
CLK2 (MHz)
CLK1 (MHz)
Figure 1. Input and Output Clock Waveforms in Zero Delay Selections
In the modes that are not Zero Delay, the phase relationship between the input and output clocks is not
predictable. Although it will not change once the MK2049-02 is running, this relationship may change
when power is interrupted.
In all modes, the output frequencies are locked to the input, and will remain at the specified output
frequency, as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output frequency remain locked.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2049-35SI | 49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-44SI | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45ASITR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45SITR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45SILFTR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-02S | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-02SI | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-02SITR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-02STR | 制造商:ICS 制造商全稱:ICS 功能描述:Communications Clock PLLs |
| MK2049-03S | 制造商:MICROCLOCK 功能描述: |
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