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參數(shù)資料
| 型號： | MK1726-01AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 32 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | TSSOP-8 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 168K |
| 代理商： | MK1726-01AGLF |
Low EMI Clock Generator
MDS 1726A B
3
Revision 101703
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
MK1726A
Pin Descriptions
External Components
The MK1726-01A/-02A/-04A devices require a
minimum number of external components for proper
operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 7 and 2. Connect the
capacitor as close to these pins as possible. For
optimum device performance, mount the decoupling
capacitor on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
Use series termination when the PCB trace between
the clock output and the load is over 1 inch. To series
terminate a 50
trace (a commonly used trace
impedance), place a 33
resistor in series with the
clock line. Place the resistor as close to the clock
output pin as possible. The nominal impedance of the
clock output is 20
.
Tri-level Select Pin Operation
The S1 and S0 select pins are tri-level, meaning that
they have three separate states to make the selections
shown in the table on page 2. To select the M (mid)
level, the connection to these pins must be eliminated
by either floating them originally, or tri-stating the GPIO
pins which drive the select pins.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, observe the following guidelines:
1) Mount the 0.01F decoupling capacitor on the
component side of the board as close to the VDD pin
as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to
the VDD pin and the PCB trace to the ground via
should be kept as short as possible.
2) To minimize EMI, place the 33
series-termination
resistor (if needed) close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, thus minimizing vias through
other signal layers. Other signal traces should be
routed away from the MK1726A devices. This includes
signal traces located underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant crystal. To
optimize the initial accuracy, connect crystal capacitors
from pins X1 to ground and X2 to ground. The value of
these capacitors is given by the following equation:
Crystal caps (pF) = (CL - 6) x 2
Pin
Number
Pin
Name
Pin Type
Pin Description
1
X1/ICLK
Input
Connect to 4-32 MHz crystal or clock.
2
GND
Power
Connect to ground.
3
S1
Input
Function select 1 input. Selects spread amount and direction per table above.
(default-internal mid-level).
4
S0
Input
Function select 0 input. Selects spread amount and direction per table above.
(default-internal mid-level).
5
SSCLK
Output
Clock output with Spread spectrum
6
FRSEL
Input
Function select for input frequency range. Default to mid level “M”.
7
VDD
Power
Connect to +3.3 V.
8
X2
XO
Crystal connection to 4-32 MHz crystal. Leave unconnected for clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK1726-02AGLF | 64 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK1726-02AG | 64 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK1726-04AGLF | 128 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK1726-01AGTRLF | 32 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK1726-04ASTRLF | 128 MHz, OTHER CLOCK GENERATOR, PDSO8 |
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