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參數(shù)資料
| 型號： | MK1725GLFT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 136 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.173 INCH, LEAD FREE, TSSOP-16 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 152K |
| 代理商： | MK1725GLFT |
Quad Output Spread Spectrum Clock Generator
MDS 1725 C
3
Revision 021605
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ●
www.icst.com
MK1725
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the
MK1725 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(CL -6)*2. In this equation, CL= crystal load capacitance
in pF. Example: For a crystal with an 18 pF load
capacitance, each crystal capacitor would be 24 pF
[(18-6) x 2] = 24.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI the 33
series termination resistor
(if needed) should be placed close to the clock outputs.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the MK1725. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
10
CLK4
Output
Clock 4 output. Frequency and spread amount are determined
by table above. Weak internal pull-down when tri-state.
11
GND
Power
Connect to ground.
12
VDD
Power
Connect to +3.3V.
13
S2
Input
Select pin 2. Determines frequency and spread amount on
output clocks as per table above. Internal pull-down.
14
PDTS
Input
Power Down Tri-state. Powers down entire chip and tri-states
outputs when low. Internal pull-up resistor.
15
VDD
Power
Connect to +3.3V.
16
X2
Input
20MHz-34MHz crystal input. Float for clock input.
Pin
Number
Pin
Name
Pin
Type
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK1726-01AGLF | 32 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK1726-02AGLF | 64 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK1726-02AG | 64 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK1726-04AGLF | 128 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MK1726-01AGTRLF | 32 MHz, OTHER CLOCK GENERATOR, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1725GLFTR | 功能描述:IC CLK GEN SPRD SPECTRUM 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| MK1726-01 SLFTR | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Single 8-Pin SOIC T/R |
| MK1726-08S | 功能描述:IC CLK GEN SPREAD SPECTRUM 8SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK1726-08SLF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SPREAD SPECTRUM CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1726-08SLFTR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SPREAD SPECTRUM CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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