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| 型號： | MF280C51-12R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 67/290頁 |
| 文件大?。?/td> | 4178K |
| 代理商： | MF280C51-12R |
Debug Interface and EmbeddedICE-RT
ARM DDI 0165B
Copyright 2000 ARM Limited. All rights reserved.
7-21
7.9
Monitor mode debug
ARM9E-S contains logic that allows the debugging of a system without stopping the
core entirely. This allows the continued servicing of critical interrupt routines while the
core is being interrogated by the debugger. Setting bit 4 of the debug control register
enables the monitor mode debug features of ARM9E-S. When this bit is set, the
EmbeddedICE-RT logic is configured so that a breakpoint or watchpoint causes the
ARM to enter abort mode, taking the Prefetch or Data Abort vectors respectively. There
are a number of restrictions you must be aware of when the ARM is configured for
monitor mode debugging:
Breakpoints and watchpoints cannot be data-dependent. No support is provided
for use of the range functionality. Breakpoints and watchpoints can only be based
on:
—
instruction or data addresses
—
external watchpoint conditioner (DBGEXTERN)
—
User or Privileged mode access (DnTRANS/InTRANS)
—
read/write access (watchpoints)
—
access size (breakpoints ITBIT, watchpoints DMAS[1:0])
—
chained comparisons.
The single-step hardware must not be enabled.
External breakpoints or watchpoints are not supported.
The vector catching hardware can be used but must not be configured to catch the
Prefetch or Data Abort exceptions.
No support is provided to mix halt mode debug and monitor mode debug
functionality.
The fact that an abort has been generated by the monitor mode is recorded in the
monitor mode debug status register in coprocessor 14 (see Comms channel monitor
Because the monitor mode debug bit does not put the ARM9E-S into debug state, it now
becomes necessary to change the contents of the watchpoint registers while external
memory accesses are taking place, rather than being changed when in debug state. In
the event that the watchpoint registers are written to during an access, all matches from
the affected watchpoint unit using the register being updated are disabled for the cycle
of the update.
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