參數(shù)資料
型號(hào): MCF54415CMJ250
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: MICROPROCESSOR, PBGA256
封裝: 12 X 12 MM, ROHS COMPLAINT, MAPBGA-256
文件頁數(shù): 52/60頁
文件大?。?/td> 1107K
代理商: MCF54415CMJ250
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 6
Preliminary—Subject to Change Without Notice
Electrical characteristics
Freescale Semiconductor
56
4.30
Debug AC timing specifications
Table 41 lists specifications for the debug AC timing parameters shown in Figure 41 and Table 42.
All debug signals use pad type pad_msr except for PSTCLK which use pad type pad_fsr. The following timing specifications
assume a pad slew rate setting of 11 and a load of 50 pF.1
Figure 41. Real-time trace AC timing
Figure 42. BDM serial port AC timing
1.These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting
(11). When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to
increase edge rise and fall times, thus reducing EMI.
Table 41. Debug AC timing specification
Num
Characteristic
Min
Max
Units
D0
PSTCLK cycle time
0.5
1/fSYS
D1
PSTCLK rising to PSTDDATA valid
3.0
ns
D2
PSTCLK rising to PSTDDATA invalid
0.5
ns
D3
DSI-to-DSCLK setup
1
PSTCLK
D41
1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative
to the rising edge of PSTCLK.
DSCLK-to-DSO hold
4
PSTCLK
D5
DSCLK cycle time
5
PSTCLK
D6
BKPT assertion time
1
PSTCLK
PSTDDATA[7:0]
D0
D1
D2
Past
Current
DSCLK
DSI
DSO
Next
Current
D5
D3
D4
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