參數(shù)資料
型號： MCC141800AZ
廠商： MOTOROLA INC
元件分類： 顯示驅(qū)動器
英文描述： LCD Segment/Common Driver
中文描述： LIQUID CRYSTAL DISPLAY DRIVER, UUC236
封裝： GOLD BUMP, DIE-236
文件頁數(shù)： 21/32頁
文件大小： 541K
代理商： MCC141800AZ
3–297
MC141800A
MOTOROLA
Data Read / Write
To read data from the GDDRAM, input High to R/W pin and D/C pin in parallel mode or pull high at the 7th and 8th bit of the address in IIC
serial mode or send Data Direction command 01001001 in SPI mode. Data is valid at the falling edge of CLK. And the GDDRAM column
address pointer will be increased by one automatically.
To write data to the GDDRAM, input Low to R/W pin and High to D/C pin in parallel mode or pull low 7th bit and high 8th bit of the address in
IIC serial mode or send Data Direction command 01001000 in SPI mode. Data is latched at the falling edge of CLK. And the GDDRAM column
address pointer will be increased by one automatically. If parallel interface is selected, End of command should be followed after all data are
send out.
No auto address pointer increment will be performed for the Dummy Write Data after Master Clear GDDRAM. (Refer to the “Commands
Required for R/W Actions on RAM” Table)
Address Increment Table (Automatic)
Address Increment is done automatically data read write. The column address pointer of GDDRAM
*3
is affected.
Remarks:
*1. Only data is read from RAM.
*2. If write data is issued after Command Clear RAM, Address increase is not applied.
*3. Column Address will wrap round when overflow.
D/C
R/W
Comment
Address Increment
Remarks
0
0
Write Command
No
0
1
Read Command
No (invalid mode)
*1
1
0
Write Data
Yes
*2
1
1
Read Data
Yes
Commands Required for R/W Actions on RAM
* No need to resend the command again if it is set previously.
The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content
whether the target RAM content is being displayed.
R/W Actions on RAMs
Commands Required
Read/Write Data from/to GDDRAM.
Set GDDRAM Page Address
Set GDDRAM Column Address
Read/Write Data
End of command
(0000X
3
X
2
X
1
X
0
)*
(1X
6
X
5
X
4
X
3
X
2
X
1
X
0
)*
(X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
)
(00111100)
Save/Restore GDDRAM Column Address.
Save/Restore GDDRAM Column Address
End of command
(0011010X
0
)
(00111100)
Master Clear GDDRAM
Set Clear Page GDDRAM (64 x 128 bits)
Dummy Write Data
(00110110)
(X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
)
(00001000)
(00110111)
(X
7
X
6
X
5
X
4
X
3
X
2
X
1
X
0
)
Master Clear Icon RAM
Set GDDRAM Page Address to Page 9
Master Clear Icon RAM (128 bits, row 64)
Dummy Write Data
COMMAND TABLE
Bit Pattern
Command
Comment
0111011X
0
Reserved
X
0
=0: Normal Operation (POR)
X
0
=1: Test Mode 2 Select
(Note: Make sure to set X
0
=0 during application)
X
0
=0: Internal oscillator (POR)
X
0
=1: External oscillator.
For internal oscillator place a resistor between OSC1 and OSC2.
For external oscillator mode, feed clock input to OSC2.
0111101X
0
Set Internal / External Oscillator
0111111X
0
Set Oscillator On/Off
X
0
=0: oscillator Off (POR)
X
0
=1: oscillator On.
This is the master control for oscillator circuitry. This command
should be issued after the “Set Internal / External Oscillator” com-
mand.
1X
6
X
5
X
4
X
3
X
2
X
1
X
0
Set GDDRAM Column Address
Set GDDRAM Column Address.
Use X
6
X
5
X
4
X
3
X
2
X
1
X
0
as address bits.
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