參數(shù)資料
型號(hào)： MCC141800AZ
廠商： MOTOROLA INC
元件分類： 顯示驅(qū)動(dòng)器
英文描述： LCD Segment/Common Driver
中文描述： LIQUID CRYSTAL DISPLAY DRIVER, UUC236
封裝： GOLD BUMP, DIE-236
文件頁(yè)數(shù)： 15/32頁(yè)
文件大小： 541K
代理商： MCC141800AZ
3–291
MC141800A
MOTOROLA
Display Timing Generator
This module is an on chip low power RC oscillator circuitry (Fig-
ure 8). The oscillator frequency can be selected in the range of
15kHz to 250kHz by external resistor. One can enable the circuitry by
software command. For external clock provided, feed the clock to
OSC2 and leave OSC1 open.
Figure 8. Oscillator Circuitry
LCD Driving Voltage Generator and Internal Regulator
This module generates the LCD voltage needed for display output.
It takes a single supply input and generate necessary bias voltages.
It consists of:
1. 4X and 5X DC-DC Converter
To generate the Vcc voltage. 4X DC-DC converter is used for LCD
panel which needs lower driving voltage for less power consump-
tion. 5X DC-DC converter is used for LCD panel which needs
higher driving voltage.
2. Internal Regulator
Feedback gain control for initial LCD voltage. it can also be used
with external contrast control.
3. Smart Bias Divider
Divide the LCD display voltage (V
LL2
-V
LL6
) from the Internal Regu-
lator output. This is a low power consumption circuit which can
save the most display current compare with traditional resistor lad-
der method.
4. Contrast Control Block
Software control of 16 voltage levels of LCD voltage.
All blocks can be individually turned off if external voltage genera-
tor is employed
5. Bias Ratio Selection circuitry
Software control of 1/7 and 1/9 bias ratio to match the characteris-
tic of LCD panel.
6. Self adjust temperature compensation circuitry
Provide 4 different compensation grade selections to satisfy the
various liquid crystal temperature grades. The grading can be
selected by software control.
65 Bit Latch / 128 Bit Latch
A register carries the display signal information. First 65 bits are
Common driving signals and other 128 bits are Segment driving sig-
nals. Data will be input to the HV-buffer Cell for bumping up to the
required level.
Level Selector
Level Selector is a control of the display synchronization. Display
voltage can be separated into two sets and used with different
cycles. Synchronization is important since it selects the required LCD
voltage level to the HV Buffer Cell for output signal voltage pump.
HV Buffer Cell (Level Shifter)
HV Buffer Cell works as a level shifter which translates the low
voltage output signal to the required driving voltage. The output is
shifted out with an internal FRM clock which comes from the Display
Timing Generator. The voltage levels are given by the level selector
which is synchronized with the internal M signal.
LCD Panel Driving Waveform
The following is an example of how the Common and Segment
drivers may be connected to a LCD panel. The waveforms shown in
Figure 9a, 9b and 9c illustrate the desired multiplex scheme.
In order to reduce the crosstalk effect, invert the polarities of the
pixel-driving waveforms every 2 or 4 or 8 or 65 lines according to the
selected waveforms. In the power-up state, the default waveform will
be type “B”.
Figure 9a. LCD Display Example “0”
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern
to be displayed. The size of the RAM is determined by number of row
times the number of column (128x65 = 8320 bits). Figure 7 is a
description of the GDDRAM address map. For mechanical flexibility,
re-mapping on both Segment and Common outputs are provided.
Oscillation Circuit
enable2
OSC1
OSC2
Feedback for internal oscillator
For external CLK input
Oscillator enable
MC141800A
External component
Buffer
enable1
enable
Internal Oscillator selected
COM1
COM2
COM3
COM4
COM5
COM6
COM7
S
S
S
S
COM0
S
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