參數(shù)資料
型號(hào)： MCC141800AZ
廠商： MOTOROLA INC
元件分類： 顯示驅(qū)動(dòng)器
英文描述： LCD Segment/Common Driver
中文描述： LIQUID CRYSTAL DISPLAY DRIVER, UUC236
封裝： GOLD BUMP, DIE-236
文件頁(yè)數(shù)： 13/32頁(yè)
文件大小： 541K
代理商： MCC141800AZ
3–289
MC141800A
MOTOROLA
OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER
Description of Block Diagram Module
Command Decoder and Command Interface
This module determines whether the input data is interpreted as
data or command. Data is directed to this module based upon the
input of the D/C pin. If D/C high, data is written to Graphic Display
Data RAM (GDDRAM). D/C low indicates that the input at D0-D7 is
interpreted as a Command.
Reset is of same function as Power ON Reset (POR). Once RES
received the reset pulse, all internal circuitry will back to its initial sta-
tus. Refer to Command Description section for more information.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D0-
D7), R/W, D/C, CE and the CLK. The R/W input High indicates a
read operation from the Graphic Display Data RAM (GDDRAM). R/W
input Low indicates a write operation to Display Data RAM or Internal
Command Registers depending on the status of D/C input. The CLK
input serves as data latch signal (clock). Refer to AC operation con-
ditions and characteristics section for Parallel Interface Timing
Description.
MPU Serial IIC Interface
The IIC interface consists of two communication bus: data pin
SDA and clock pin CLK. The CLK input serves as data latch signal
(clock). Before communication begins, a start condition must be
setup on the bus by the controller. To establish a start condition, the
controller must pull the data pin low while the clock pin is high.
After the start condition has been established for t
HSTART
, an
eight-bit address should be sent. The six most significant bits of the
address (0111xy) are used to uniquely define devices on the bus, the
7th bit is used as a data / command control: if it is 0, then the signal
on SDA is interpreted as a command; if it is 1, then data SDA is writ-
ten to GDDRAM. The least significant bit is a data direction read /
write control; if it is 0, then the controller writes data / command to the
driver; if it is 1, then the controller reads data / command from LCD
driver.
Data is transferred with the most significant bit first. Each byte has
to be followed by an acknowledge bit. The transmitter releases the
SDA high during the acknowledge clock pulse. The receiver has to
pull down the SDA during the acknowledge clock pulse.
To end communication, a stop condition should be set up on the
bus. A low to high transition of data pin while the clock pin is high
defines a stop condition. However, if a master still wishes to commu-
nicate on the bus, another start condition and address can be gener-
ated without a stop condition. Refer to AC operation conditions and
characteristics section for IIC Serial Interface Timing Description.
MPU Serial Peripheral Interface
The SPI consists of 4 communication bus: data input pin Din, data
output pin Dout, clock pin CLK and chip enable pin CE. The CLK
input serves as data latch signal (clock).
Data is transferred serially with most significant bit first, least sig-
nificant bit last. During the communication, the controller must input
Low CE before data transactions and must stay low for the rest of the
transaction. By default, the LCD driver will receive command from
MCU. If messages on the data pin are data rather than command,
MCU should send Data Direction command (0100100X
0
) to control
the data direction and then one more command to define the number
of data bytes will be read / write. After these two continuous com-
mands are send, the following messages will be data rather than
command. For read operation (X
0
= 1), MCU reads a group of data
from LCD driver through Dout pin. For write operation (X
0
= 0), MCU
writes a group of data to the LCD driver through Din pin. Refer to AC
operation conditions and characteristics section for Serial Peripheral
Interface Timing Description.
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