參數(shù)資料
型號: MC9328MX21VM
廠商: Freescale Semiconductor
文件頁數(shù): 39/100頁
文件大小: 0K
描述: IC MCU I.MX21 266MHZ 289-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: i.MX21
核心處理器: ARM9
芯體尺寸: 32-位
速度: 266MHz
連通性: 1 線,EBI/EMI,I²C,IrDA,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 192
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.45 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 289-LFBGA
包裝: 托盤
Specifications
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
43
3.13
External Memory Interface (EMI) Electricals
3.13.1
NAND-Flash Controller (NFC) Interface
Figure 33, Figure 34, Figure 35, and Figure 36 depict the relative timing requirements among different
signals of the NFC at module level, and Table 29 lists the timing parameters. The NAND Flash Controller
(NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module,
where time T is the period of the NFC clock in ns. Per the i.MX21 Reference Manual, specifically the
Phase-Locked (PLL), Clock, and Reset Controller chapter, the NFC clock is derived from the same clock
which drives the CPU clock (FCLK) that is fed through the NFCDIV block to generate the NFC clock.
The relationship between the NFC clock and the external timing parameters of the NFC is provided in
Table 29 also provides two examples of external timing parameters with NFC clock frequencies of
22.17 MHz and 33.25 MHz. For example, assuming a 266 MHz FCLK (CPU clock), NFCDIV should be
set to divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC
clock. The user should compare the parameters of the selected NAND Flash memory with the NFC
external timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is
66 MHz. It should also be noted that the default NFC clock on power up is 16.63 MHz.
Figure 33. Command Latch Cycle Timing DIagram
NFCLE
NFCE
NFWE
NFALE
NFIO[7:0]
command
NF9
NF8
NF1
NF2
NF5
NF3
NF4
NF6
NF7
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