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參數(shù)資料
| 型號(hào)： | MC74HC86D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-Terminal 0.1A Postive Voltage Regulator; Package: TO-92R; No of Pins: 3; Container: Bulk |
| 中文描述： | HC/UH SERIES, QUAD 2-INPUT XOR GATE, PDSO14 |
| 封裝： | PLASTIC, SOIC-14 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 163K |
| 代理商： | MC74HC86D |
MC54/74HC86
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
tPHL
(Figures 1 and 2)
4.5
24
36
6.0
13
30
19
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
—
10
16
10
pF
10
CPD
Power Dissipation Capacitance (Per Gate)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
33
pF
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 1. Switching Waveforms
Figure 2. Test Circuit
OUTPUT Y
INPUT
A OR B
90%
50%
10%
tTLH
tTHL
tPLH
tPHL
tr
tf
GND
VCC
90%
50%
10%
A
B
Y
EXPANDED LOGIC DIAGRAM
(1/4 of Device)
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