參數(shù)資料
型號(hào): MC74HC86AN
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Quad 2-Input Exclusive OR Gate
中文描述: HC/UH SERIES, QUAD 2-INPUT XOR GATE, PDIP14
封裝: PLASTIC, DIP-14
文件頁(yè)數(shù): 2/6頁(yè)
文件大小: 145K
代理商: MC74HC86AN
MC54/74HC86A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
2
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Tstg
Storage Temperature
TL
Lead Temperature, 1 mm from Case for 10 Seconds
V
TSSOP Package
300
450
mW
– 65 to + 150
C
(Ceramic DIP)
C
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
1000
500
400
ns
Symbol
b l
Parameter
Test Conditions
di i
V
25 C
U i
3.0
6.0
4.2
3.98
4.2
1.8
125 C
4.2
1.8
5.9
Voltage
6.0
6.0
|Iout|
20
μ
A
5.9
2.1
2.1
2.1
Maximum Low–Level Input
Voltage
|Iout|
20
μ
A
2.0
3.0
0.5
0.9
0.5
0.9
1.8
0.5
0.9
V
Minimum High–Level Output
Voltage
|Iout|
20
μ
A
2.0
1.9
3.70
1.9
5.9
1.9
V
|Iout|
4.5
3.84
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
(Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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