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參數(shù)資料
| 型號(hào)： | MC74HC237N |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1-of-8 Decoder/Demultiplexer with Address Latch |
| 中文描述： | HC/UH SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 205K |
| 代理商： | MC74HC237N |
MC74HC237
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is enabled,
determine which of the eight outputs is selected.
CONTROL INPUTS
CS1, CS2 (Pins 6, 5)
Chip select inputs. For CS1 at a high level and CS2 at a
low level, the chip is enabled and the outputs follow the data
inputs (Latch Enable = L). For any other combination of CS1
and CS2, the outputs are at a low level.
Latch Enable (Pin 4)
Latch Enable input. A high level at this input latches the
Address. A low level at this input allows the outputs to follow
the Address (CS1 = H and CS2 = L).
OUTPUTS
Y0–Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
Active–high outputs. One of these eight outputs is selected
when the chip is enabled (CS1 = H and CS2 = L) and the
Address inputs correspond to that particular output. The
selected output is at a high level while all others remain at a
low level.
SWITCHING WAVEFORMS
Figure 1.
50%
INPUT A
LATCH ENABLE
VCC
Figure 2.
VALID
GND
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3.
VCC
GND
tsu
th
50%
Figure 4.
INPUT A
OUTPUT Y
VALID
VALID
VCC
GND
50%
50%
tPLH
tPHL
CS2
OUTPUT Y
90%
50%
10%
90%
50%
10%
tf
tr
VCC
GND
tPHL
tPLH
tTLH
tTHL
CS1
OUTPUT Y
tr
tf
VCC
GND
90%
50%
10%
90%
50%
10%
tPHL
tPLH
tTLH
tTHL
LATCH
ENABLE
OUTPUT Y
tw
50%
50%
VCC
GND
tPHL
tPLH
50%
Figure 5.
Figure 6. Test Circuit
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