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| 型號： | MC68L11FC0FU3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 21/68頁 |
| 文件大小： | 486K |
| 代理商： | MC68L11FC0FU3 |
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MC68HC11F1/FC0
MC68HC11FTS/D
MOTOROLA
21
RBOOT — Read Bootstrap ROM
RBOOT is valid only when SMOD is set to one (special bootstrap or special test mode). RBOOT can
only be written in special modes but can be read anytime.
0 = Boot loader ROM disabled and not in memory map
1 = Boot loader ROM enabled and in memory map at $BF00–$BFFF
SMOD and MDA
—
Special Mode Select and Mode Select A
The initial value of SMOD is the inverseof the logic level present on the MODB pin at the rising edge
of reset. The initial value of MDA equalsthe logic level present on the MODA pin at the rising edge of
reset. These two bits can be read at any time. They can be written at any time in special modes. Neither
bit can be written in normal modes. SMOD cannot be set once it has been cleared. Refer to
Table 8
.
IRV — Internal Read Visibility
This bit can be read at any time. It can be written at any time in special modes, but only once in normal
modes. In single-chip and bootstrap modes, IRV has no meaning or effect.
0 = Internal reads not visible
1 = Data from internal reads is driven on the external data bus
PSEL[3:0] — See
5.2 Reset and Interrupt Registers
, page 27.
The INIT register can be written only once in first 64 cycles out of reset in normal modes, or at any time
in special modes.
NOTE
The register diagram above applies to the MC68HC11FC0 only. A diagram and bit
descriptions of the INIT register in the MC68HC11F1 are provided elsewhere in
this section.
RAM[5:0] — Internal RAM Map Position
These bits determine the upper six bits of the RAM address and allow mapping of the RAM to any one-
Kbyte boundary.
REG[1:0] — Register Block Map Position
These bits determine the location of the register block, as shown in
Table 9
.
Table 8 Hardware Mode Select Summary
Input Pins
MODB
1
1
0
0
Mode Description
Control Bits in HPRIO (Latched at Reset)
RBOOT
SMOD
0
0
0
0
1
1
0
1
MODA
0
1
0
1
MDA
0
1
0
1
Single Chip
Expanded
Special Bootstrap
Special Test
INIT —
RAM and I/O Mapping (
MC68HC11FC0 only
)
$x03D
Bit 7
6
5
4
3
2
1
Bit 0
RAM5
RAM4
RAM3
RAM2
RAM1
RAM0
REG1
REG0
RESET:
0
0
0
0
0
0
0
1
Table 9 Register Block Location
REG[1:0]
0 0
0 1
1 0
1 1
Register Block Address
$0000 – $005F
$1000 – $105F
$2000 – $205F
$3000 – $305F
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