參數(shù)資料
型號: MC68HRC908JL3MP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: CA-BAYONET
中文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 62/83頁
文件大?。?/td> 1923K
代理商: MC68HRC908JL3MP
Central Processor Unit (CPU)
Technical Data
MC68H(R)C908JL3
Rev. 1.0
62
Central Processor Unit (CPU)
MOTOROLA
BRCLR noprrel Branch if Bit nin M Clear
PC
(PC) + 3 + rel (Mn) = 0
– – – – –
¤
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel
Branch Never
PC
(PC) + 2
– – – – – – REL
21
rr
3
BRSET noprrel Branch if Bit nin M Set
PC
(PC) + 3 + rel (Mn) = 1
– – – – –
¤
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET nopr
Set Bit n n M
Mn
1
– – – – – –
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
BSR rel
Branch to Subroutine
PC
(PC) + 2; push (PCL)
SP
(SP) – 1; push (PCH)
SP
(SP) – 1
PC
(PC) + rel
– – – – – – REL
AD
rr
4
CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel
Compare and Branch if Equal
PC
(PC) + 3 + rel (A) – (M) = $00
PC
(PC) + 3 + rel (A) – (M) = $00
PC
(PC) + 3 + rel (X) – (M) = $00
PC
(PC) + 3 + rel (A) – (M) = $00
PC
(PC) + 2 + rel (A) – (M) = $00
PC
(PC) + 4 + rel (A) – (M) = $00
– – – – – –
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
4
6
CLC
Clear Carry Bit
C
0
– – – – – 0 INH
98
1
CLI
Clear Interrupt Mask
I
0
– – 0 – – – INH
9A
2
CLR opr
CLRA
CLRX
CLRH
CLR oprX
CLR ,X
CLR oprSP
Clear
M
$00
A
$00
X
$00
H
$00
M
$00
M
$00
M
$00
0 – – 0 1 –
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E6F
dd
ff
ff
3
1
1
1
3
2
4
Table 6-1. Instruction Set Summary
Source
Form
Operation
Description
Effect on
CCR
A
M
O
O
C
V H I N Z C
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