參數(shù)資料
型號(hào): MC68HRC908JL3CP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: MC68HC908JK1
中文描述: 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 59/83頁
文件大小: 1923K
代理商: MC68HRC908JL3CP
Central Processor Unit (CPU)
CPU During Break Interrupts
MC68H(R)C908JL3
Rev. 1.0
Technical Data
MOTOROLA
Central Processor Unit (CPU)
59
6.6.2 Stop Mode
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
6.9 Opcode Map
See
Table 6-2
.
相關(guān)PDF資料
PDF描述
MC68RHC908JK1 MC68HC908JK1
MC68HRC908JL3MP CA-BAYONET
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