參數(shù)資料
型號: MC14583BCL
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Dual Schmitt Trigger
中文描述: 4000/14000/40000 SERIES, DUAL 1-INPUT INV/NINV GATE, CDIP16
封裝: CERAMIC, DIP-16
文件頁數(shù): 1/8頁
文件大?。?/td> 224K
代理商: MC14583BCL
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14583B
The MC14583B is a dual Schmitt trigger constructed with complementary
P–channel and N–channel MOS devices on a monolithic silicon substrate.
Each Schmitt trigger is functionally independent except for a common
3–state input and an internally–connected Exclusive OR output for use in
line receiver applications. Trigger levels are adjustable through the positive,
negative, and common terminals with the use of external resistors.
Applications include the speed–up of a slow waveform edge in interface
receivers, level detectors, etc.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Single Supply Operation
Capable of Driving Two Low–power TTL Loads or One Low–power
Resistor Adjustable Trigger Levels
VDD
Vin, Vout
Iin, Iout
DC Supply Voltage
– 0.5 to + 18.0
V
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
±
10
V
Input or Output Current (DC or Transient),
per Pin
mA
PD
Tstg
TL
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
LOGIC DIAGRAM
POSITIVE A
6 5
NEGATIVE A
7 COMMON A
Bout
9
Ain
12
Bout
10
EXCLUSIVE OR
14
Aout
11
Aout
4
13
15
Bin
POSITIVE B2
2 3
NEGATIVE B
1 COMMON B
3–STATE
OUTPUT DISABLE
VDD = PIN 16
VSS = PIN 8
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
BLOCK DIAGRAM
TRUTH TABLE
Inputs
Outputs
A
B
Dis
Aout AoutBoutBout
0
Z
0
1
0
Z
0
1
1
Z
1
0
1
Z
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
Z
1
Z
0
Z
1
Z
0
0
0
1
1
1
1
0
0
Z = High impedance at output
VDD = PIN 16
VSS = PIN 8
9
13
15
12
10
14
11
4
APosANegACom
BPosBNegBCom
Ain
Bin
Dis
Bout
Bout
Aout
Aout
6
5
7
2
3
1
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