- 您現(xiàn)在的位置：買賣IC網 > PDF目錄379307 > MC145750 (Motorola, Inc.) QPSK Encoder PDF資料下載
參數(shù)資料
| 型號： | MC145750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | QPSK Encoder |
| 中文描述： | 調制編碼器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 296K |
| 代理商： | MC145750 |
MC145750
MOTOROLA
7
DEVICE DESCRIPTION
π
/4–Shift QPSK Encoding
RCR standard (STD–28) specifies the basic configuration
of this modulation scheme as shown in Figure 2. First, serial
data input is converted to Xk/Yk parallel streams. Then its
value is compared with one previous symbol Ik/Qk, respec-
tively, whether or not there is a change of polarity. If there is a
change, result is coded as 1. This two–bit
π
r (di–bit) is called
symbol, hence symbol rate is just half of the data input rate to
be modulated.
Phase transitions are determined as shown in Figure 3,
with respect to four di–bit values of Xk, Yk. (As is shown,
there should be at least
π
/4 of phase shift in each symbol tim-
ing unlike plain QPSK.) Actual in–phase outputs are fed to a
quadrature modulator circuit, and it is recommended that a
2– to 3–order LPF be used, which may be used as a level
shifter and dc offset compensation circuitry at the same time.
The reference voltage for the DACs is given by connecting
either of DAref1:3 to VDD according to the operating voltage
used. It is preferable not to have this voltage vary, since I/Q
output levels are affected.
Timing Generator
The PLL is intended in order to generate all required timing
signals for the devices. The VCO oscillating at the PN511
pattern rate is utilized when some characteristics are mea-
sured. By pulling MODE0 pin high, the device generates this
sequence. It is a useful simple measurement for the occu-
pied power bandwidth and the out–of–band power level. The
sequence itself can also be monitored at the PNO pin.
This circuit is reset by an external reset signal while the
low–state of DS is not valid for initializing the generator.
START–UP SEQUENCE
To ensure stability and to initialize the internal ROM and
encoder, the start–up sequence should be done at power–
up. Refer to Figure 4.
Di–Bit Input
Xk
Yk
Phase Shift
0
0
1
1
0
1
0
1
π
/4
3
π
/4
–
π
/4
– 3
π
/4
Figure 3. Phase Diagram
Q
00
01
11
10
I
22.5
°
Figure 4. Start–Up Sequence
VDD
REST/PDN
DS
90%
> 100
μ
s
1 s
相關PDF資料 |
PDF描述 |
|---|---|
| MC1490 | WIDEBAND AMPLIFIER WITH AGC |
| MC1490D | OC-48,24,12 SONET SDH Multi-rate Transceiver 100-HTQFP -40 to 85 |
| MC1490P | 2.7 Gbps OC-48 SONET Transceiver 100-HTQFP -40 to 85 |
| MC1648 | Voltage Controlled Oscillator |
| MC1648D | Voltage Controlled Oscillator |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC14575CL | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MC14575CP | 制造商: 功能描述: 制造商:Motorola Inc 功能描述: 制造商:undefined 功能描述: |
| MC14576CFEL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC14577CF | 制造商:Freescale Semiconductor 功能描述: |
| MC14577CFEL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。