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參數(shù)資料
| 型號(hào)： | MC14568BD |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Phase Comparator and Programmable Counters |
| 中文描述： | 4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED UP DIVIDE BY N COUNTER, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 323K |
| 代理商： | MC14568BD |
MOTOROLA CMOS LOGIC DATA
7
MC14568B
OPERATING CHARACTERISTICS
The MC14568B contains a phase comparator, a fixed
divider (
÷
4,
÷
16,
÷
64,
÷
100) and a programmable divide–
by–N 4–bit counter.
PHASE COMPARATOR
The phase comparator is a positive edge controlled logic
circuit. It essentially consists of four flip–flops and an output
pair of MOS transistors. Only one of its inputs (PCin, pin 14)
is accessible externally. The second is connected to the out-
put of one of the two counters D1 or D2 (see block diagram).
Duty cycles of both input signals (at A and B) need not be
taken into consideration since the comparator responds to
leading edges only.
If both input signals have identical frequencies but different
phases, with signal A (pin 14) leading signal B (Ref.), the
comparator output will be high for the time equal to the
phased difference.
If signal A lags signal B, the output will be low for the same
time. In between, the output will be in a three–state condition
and the voltage on the capacitor of an RC filter normally con-
nected at this point will have some intermediate value (see
Figure 4). When used in a phase locked loop, this value will
adjust the Voltage Controlled Oscillator frequency by reduc-
ing the phase difference between the reference signal and
the divided VCO frequency to zero.
Figure 4. Phase Comparator Waveforms
A (PCin)
B (REF.)
PCout
LD
VDD
VSS
VOH
VOL
VOH
VOL
VOH
VOL
1/f
If the input signals have different frequencies, the output
signal will be high when signal B has a lower frequency than
signal A, and low otherwise.
Under the same conditions of frequency difference, the
output will vary between VOH (or VOL) and some intermedi-
ate value until the frequencies of both signals are equal and
their phase difference equal to zero, i.e. until locked condition
is obtained.
Capture and lock range will be determined by the VCO fre-
quency range. The comparator is provided with a lock indi-
cator output, which will stay at logic 1 in locked conditions.
The state diagram (Figure 5) depicts the internal state
transitions. It assumes that only one transition on either sig-
nal occurs at any time. It shows that a change of the output
state is always associated with a positive transition of either
signal. For a negative transition, the output does not change
state. A positive transition may not cause the output to
change, this happens when the signals have different fre-
quencies.
DIVIDE BY 4, 16, 64 OR 100 COUNTER (D1)
This counter is able to work at an input frequency of 5 MHz
for a VDD value of 10 volts over the standard temperature
range when dividing by 4, 64 and 100. Programming is ac-
complished by use of inputs F and G (pins 10 and 11) ac-
cording to the truth table shown. Connecting the Control
input (CTL, pin 15), to VDD allows cascading this counter with
the programmable divide–by–N counter provided in the
same package. Independent operation is obtained when the
Control input is connected to VSS.
The different division ratios have been chosen to generate
the reference frequencies corresponding to the channel
spacings normally required in frequency synthesizer applica-
tions. For example. with the division ratio 100 and a 5 MHz
crystal stabilized source a reference frequency of 50 kHz is
supplied to the comparator. The lower division ratios permit
operation with low frequency crystals.
Figure 5. Phase Comparator State Diagram
00
11
10
01
00
11
01
10
00
11
10
01
INPUT STATE
PCout
LD
(LOCK DETECT)
0
0
3–STATE
OUTPUT DISCONNECTED
1
1
0
X X
A
B
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| MC14569BCL | 制造商:Motorola Inc 功能描述: |
| MC14569BCP | 功能描述:計(jì)數(shù)器移位寄存器 3-18V Divide-By-N RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14569BCPG | 功能描述:計(jì)數(shù)器移位寄存器 3-18V Divide-By-N Dual 4-Bit Binary RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14569BCPG | 制造商:ON Semiconductor 功能描述:Package/Case:16-PDIP |
| MC14569BDW | 功能描述:計(jì)數(shù)器 IC 3-18V Divide-By-N RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
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