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參數(shù)資料
| 型號： | MC14554B |
| 廠商： | Motorola, Inc. |
| 英文描述： | Single Channel (1.8V) SVS with /MR in 5/SOT23 5-SOT-23 -40 to 85 |
| 中文描述： | 2位2位并行二進制乘法器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 170K |
| 代理商： | MC14554B |
MOTOROLA CMOS LOGIC DATA
3
MC14554B
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time
K0 to C0
tPLH, tPHL = (1.7 ns/pF) CL + 185 ns
tPLH, tPHL = (0.66 ns/pF) CL + 82 ns
tPLH, tPHL = (0.5 ns/pF) CL + 60 ns
M0 to S2
tPLH, tPHL = (1.7 ns/pF) CL + 595 ns
tPLH, tPHL = (0.66 ns/pF) CL + 247 ns
tPLH, tPHL = (0.5 ns/pF) CL + 185 ns
* The formulas given are for the typical characteristics only at 25 C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
tTLH,
tTHL
5.0
10
15
—
—
100
50
40
200
100
80
ns
tPLH,
tPHL
5.0
10
15
5.0
10
15
—
—
—
—
—
—
270
115
85
680
280
210
675
290
215
1700
750
570
ns
Figure 1. Dynamic Power Dissipation
Waveforms
Figure 2. Dynamic Signal Waveforms
All outputs connected to respective
CL loads. f = system clock frequency
LOGIC DIAGRAM
MULTIPLIER CELL
Inputs X0, X1, Y0, Y1, K1, and M2 low, and inputs
M0 and M1 high.
For M0 to S2:
MULTIPLIER
CELL
C
20 ns
20 ns
VDD
VSS
VOH
VOL
90%
50%
10%
2f
1
ALL INPUTS
(50% DUTY CYCLE)
ANY OUTPUT
(50% DUTY CYCLE)
VDD
VSS
VOH
VOL
20 ns
20 ns
90%
50%
10%
tPLH
tPHL
50%
90%
10%
tTLH
tTHL
OUTPUT
C0 OR S2
INPUT
K0 OR M0
M1
Y1
M0
Y0
4
5
M2
C0
X0
K0
14
12
3
2
1
15
M
Y
M
Y
X
X
K
K
S
C
S
MULTIPLIER
CELL
M
X
K
S
C
Y
M
X
K
S
C
Y
MULTIPLIER
CELL
MULTIPLIER
CELL
6
7
9
11
S2
S1
S0
C1(S3)
X1
K1
M
Y
X
K
L
S
C
For K0 to C0:
Inputs X1, Y1, and K0 low, and inputs X0, Y0,
K1, M1, and M2 high.
13
10
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|---|---|
| MC14554 | 2-Bit by 2-Bit Parallel Binary Multiplier |
| MC145554 | Single Channel (1.2V) SVS w/ Watchdog and /MR in 5/SOT23 5-SOT-23 -40 to 85 |
| MC14555 | Dual Binary to 1-of-4 Decoder/Demultiplexer |
| MC14555B | Dual Binary to 1-of-4 Decoder/Demultiplexer |
| MC14555BCP | Dual Binary to 1-of-4 Decoder/Demultiplexer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145554DW | 制造商:Rochester Electronics LLC 功能描述:PCM CODEC-FILTER - Bulk |
| MC145554DWR2 | 制造商:Rochester Electronics LLC 功能描述:MONOCIRCUIT - Bulk |
| MC145554P | 制造商:Rochester Electronics LLC 功能描述:PCM CODEC-FILTER - Bulk |
| MC145557P | 制造商:Rochester Electronics LLC 功能描述:PCM CODEC - FILTER - Bulk |
| MC14555BCP | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-18V Dual Binary to RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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