參數(shù)資料
型號: MC145202F
廠商: MOTOROLA INC
元件分類: XO, clock
英文描述: Low-Voltage 2.0 GHz PLL Frequency Synthesizer
中文描述: PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20
封裝: SOG-20
文件頁數(shù): 7/24頁
文件大?。?/td> 343K
代理商: MC145202F
MC145202
MOTOROLA
7
LOOP SPECIFICATIONS
(VDD = VCC = 2.7 to 5.5 V unless otherwise indicated, TA = – 40 to + 85
°
C)
Symbol
b l
Parameter
Test Condition
di i
Fig.
No.
Guaranteed
Operating
Range
U i
Unit
Min
Max
Pin
fref
Input Sensitivity Range, fin
Input Frequency, REFin Externally Driven in
Reference Mode
500 MHz
fin
2000 MHz
Vin
400 mV p–p
7
– 10
4
dBm*
2.7
VDD < 4.5 V
4.5
VDD
5.5 V
8
1.5
1.5
20
30
MHz
fXTAL
Crystal Frequency, Crystal Mode
C1
30 pF, C2
30 pF, Includes Stray
Capacitance
9
2
15
MHz
fout
f
Output Frequency, REFout
Operating Frequency of the Phase Detectors
CL = 20 pF, Vout
1 V p–p
10, 12
dc
10
MHz
dc
2
MHz
tw
Output Pulse Width (
φ
R,
φ
V, and LD)
fR in Phase with fV, CL = 20 pF,
φ
R and
φ
V
active for LD measurement, **
VPD = 2.7 to 5.5 V
VDD = 2.7 V
VDD = 4.5 V
VDD = 5.5 V
11, 12
40
18
14
120
60
50
ns
tTLH,
tTHL
Output Transition Times (LD,
φ
V, and
φ
R)
CL = 20 pF, VPD = 2.7 V,
VDD = VCC = 2.7 V
11, 12
80
ns
Cin
*Power level at the input to the dc block.
**When PDout is active, LD minimum pulse width is approximately 5 ns.
Input Capacitance, REFin
7
pF
Figure 7. Test Circuit
SINE WAVE
GENERATOR
50
DEVICE
UNDER
TEST
0.01
μ
F
TEST
POINT
VCC
VDD
REFin
GND
OUTPUT A
Vin
Figure 8. Test Circuit — Reference Mode
(fR)
TEST
POINT
REFout
V+
DEVICE UNDER
TEST
C1
TEST
POINT
VCC
VDD
OUTPUT A
GND
REFin
REFout
C2
Figure 9. Test Circuit — Crystal Mode
(fR)
V+
50%
REFout
1/f REFout
Figure 10. Switching Waveform
10%
90%
OUTPUT
tTLH
tTHL
Figure 11. Switching Waveform
50%
tw
TEST POINT
DEVICE
UNDER
TEST
CL*
* Includes all probe and
fixture capacitance.
Figure 12. Test Circuit
DC
BLOCK
50
PAD
SINE WAVE
GENERATOR
50
VCC
VDD
GND
V+
TEST
POINT
OUTPUT A
(fV)
DEVICE
UNDER
TEST
fin
fin
NOTE: Alternately, the 50
pad may be a T network.
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