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| 型號： | MC145202EVK |
| 廠商： | Motorola, Inc. |
| 英文描述： | Evaluation Board Manual |
| 中文描述： | 評估板手冊 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 343K |
| 代理商： | MC145202EVK |
MC145202
MOTOROLA
5
AC INTERFACE CHARACTERISTICS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85
°
C, CL = 25 pF, Input tr = tf = 10 ns; VPD = 2.7 to 5.5 V)
Symbol
Parameter
Figure
No.
Guaranteed
Limit
Unit
fclk
Serial Data Clock Frequency (Note: Refer to Clock tw below)
Maximum Propagation Delay, CLK to OUTPUT A (Selected as Data Out)
1
dc to 4.0
MHz
tPLH, tPHL
tPLH, tPHL
tPZL, tPLZ
tTLH, tTHL
Cin
1, 5
100
ns
Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port)
2, 5
150
ns
Maximum Propagation Delay, ENB to OUTPUT B
2, 6
150
ns
Maximum Output Transition Time, OUTPUT A and OUTPUT B; tTHLonly, on OUTPUT B
Maximum Input Capacitance – Din, ENB, CLK
1, 5, 6
50
ns
10
pF
TIMING REQUIREMENTS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85
°
C, Input tr = tf = 10 ns, unless otherwise indicated)
Symbol
Parameter
Figure
No.
Guaranteed
Limit
Unit
tsu, th
tsu, th, trec
tw
tw
tr, tf
* The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.
Minimum Setup and Hold Times, Din vs CLK
Minimum Setup, Hold and Recovery Times, ENB vs CLK
3
50
ns
4
100
*
125
ns
Minimum Pulse Width, ENB
4
cycles
Minimum Pulse Width, CLK
1
ns
Maximum Input Rise and Fall Times, CLK
1
100
μ
s
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