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| 型號： | MC145202DT |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Low-Voltage 2.0 GHz PLL Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 343K |
| 代理商： | MC145202DT |
MC145202
MOTOROLA
17
DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a ref-
erence frequency to Motorola’s CMOS frequency synthe-
sizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
dc coupled to REFin. If the oscillator does not have CMOS
logic levels on the outputs, capacitive or ac coupling to REFin
may be used (see Figure 8).
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Elec-
tronic Engineers Master Catalog,the Gold Book,or similar
publications.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
REFin (see Figure 8). For large amplitude signals (standard
CMOS logic levels), dc coupling may be used.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an ap-
propriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 18.
The crystal should be specified for a loading capacitance
(CL) which does not exceed approximately 20 pF when used
at the highest operating frequencies listed in the Loop Speci-
fications table. Assuming R1 = 0
, the shunt load capaci-
tance (CL) presented across the crystal can be estimated to
be:
CinCout
Cin + Cout
where
Cin = 5 pF (see Figure 19)
Cout = 6 pF (see Figure 19)
Ca = 1 pF (see Figure 19)
C1 and C2 = external capacitors (see Figure 18)
Cstray = the total equivalent external circuit stray
capacitance appearing across the crystal
terminals
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the REFin
and REFout pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. Circuit stray
capacitance can also be handled by adding the appropriate
stray value to the values for Cin and Cout. For this approach,
the term Cstray becomes 0 in the above expression for CL.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 20. The maximum drive level specified
CL =
+ Ca + Cstray +C1
C2
C1 + C2
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
shift in operating frequency. R1 in Figure 18 limits the drive
level. The use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
frequency (fR) at OUTPUT A as a function of supply voltage.
(REFout is not used because loading impacts the oscillator.)
The frequency should increase very slightly as the dc supply
voltage is increased. An overdriven crystal decreases in fre-
quency or becomes unstable with an increase in supply volt-
age. The operating supply voltage must be reduced or R1
must be increased in value if the overdriven condition exists.
The user should note that the oscillator start–up time is pro-
portional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have devel-
oped expertise in CMOS oscillator design with crystals. Dis-
cussions with such manufacturers can prove very helpful
(see Table 6).
R1*
C2
C1
FREQUENCY SYNTHESIZER
REFout
REFin
Rf
* May be needed in certain cases. See text.
Figure 18. Pierce Crystal Oscillator Circuit
Cin
Cout
Ca
REFin
REFout
Cstray
Figure 19. Parasitic Capacitances of the
Amplifier and Cstray
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
2
1
2
1
2
1
RS
LS
CS
Re
Xe
CO
Figure 20. Equivalent Crystal Networks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC145202EVK | Evaluation Board Manual |
| MC145202F | Low-Voltage 2.0 GHz PLL Frequency Synthesizer |
| MC14522BCL | Non-inverting Fast Synchronous Buck MOSFET Drivers with Enable 14-HTSSOP |
| MC14522BCP | Presettable 4-Bit Down Counters |
| MC14522BDW | Presettable 4-Bit Down Counters |
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| MC14520B | 制造商:Motorola Inc 功能描述: 制造商:ON Semiconductor 功能描述: |
| MC14520BAL | 制造商:Motorola Inc 功能描述:Counter, Up, 4 Bit Binary, 16 Pin, Ceramic, DIP |
| MC14520BCP | 功能描述:計數(shù)器移位寄存器 3-18V Dual BCD Up RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14520BCPG | 功能描述:計數(shù)器移位寄存器 3-18V Dual BCD Up RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14520BDW | 功能描述:計數(shù)器移位寄存器 3-18V Dual BCD Up RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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