參數(shù)資料
型號: MC145173DW
廠商: MOTOROLA INC
元件分類: XO, clock
英文描述: Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter
中文描述: PLL FREQUENCY SYNTHESIZER, 130 MHz, PDSO24
封裝: SOG-24
文件頁數(shù): 9/33頁
文件大?。?/td> 277K
代理商: MC145173DW
MC145173
9
MOTOROLA
The switch point is precisely controlled by use of a
comparator. The reference for the comparator is internally
set to approximately 33% of VDD. The input has a small
amount of hysteresis voltage (approximately 50 mV).
If not used, this pin should be tied to VDD or VSS.
Input D
Digital Input (Pin 6)
Input D is a general–purpose digital input which may be
used for MCU port expansion. The state of this input is indi-
cated by the In D bit in both the A and F registers. That is, the
state of the pin may be read from either register. (See Fig-
ures 21 and 22.)
This pin is a standard CMOS input with a switch point at
approximately 50% of VDD. Input D has a hysteresis voltage
of approximately 600 mV.
If not used, this pin should be tied to VDD or VSS.
Output A
Open–Drain Digital Output (Pin 12)
Output A is a general–purpose digital output which may be
used for MCU port expansion. An N–channel MOSFET tied
to VSS is used to drive this open–drain output. Thus, an ex-
ternal pull–up device is required at this pin. The state of this
output is determined by the Out A bit in the C register. (See
Figure 17.)
Upon power–up, this pin is low. If not used, Output A
should be tied to VSS or floated.
Output B
Digital Output (Pin 13)
Output B is a general–purpose digital output which may be
used for MCU port expansion. This is a standard totem–pole
(push–pull) CMOS output. The state of this output is deter-
mined by the Out B bit in the C register. (See Figure 17.)
Upon power–up, this pin is low. If not used, Output B
should be floated.
Output C
Digital Output (Pin 14)
Output C is a general–purpose digital output which may be
used for MCU port expansion. This is a standard totem–pole
(push–pull) CMOS output. The state of this output is deter-
mined by the Out C bit in the C register. (See Figure 17.)
Upon power–up, this pin is low. If not used, Output C
should be floated.
Output D
Digital Output (Pin 22)
Output D is a general–purpose digital output which may be
used for MCU port expansion. This is a standard totem–pole
(push–pull) CMOS output. The state of this output is deter-
mined by the Out D bit in the R register. (See Figure 18.)
Upon power–up, this pin is low. If not used, Output D
should be floated.
ADC INPUT PINS
Input A, Input B
Analog Inputs (Pins 9, 8)
These are inputs to the 2–channel multiplexer which feeds
the 6–bit analog–to–digital converter (ADC). The selected
channel is determined by the Chan bit in the C register.
Each pin is a high–impedance input which appears as
a mostly–capacitive load of approximately 6 pF.
If not used, these pins should be tied to VSS or VDD.
REFERENCE PINS
OSCin/OSCout
Reference Oscillator Input/Output (Pins 1, 24)
These pins form a reference oscillator when connected to
terminals of an external parallel–resonant crystal. Frequen-
cy–setting capacitors of appropriate values as recom-
mended by the crystal supplier are connected from each pin
to ground (up to a maximum of 30 pF each, including stray
capacitance). An external feedback resistor of 1 to 10 M
is
connected directly across the pins to ensure linear operation
of the amplifier. The MC145173 is designed to operate with
crystals from 2 to 15 MHz. However, frequencies are re-
stricted to 9.5 to 10.4 MHz when the ADC is utilized. (See
Figure 13.)
If desired, an external clock source can be ac coupled to
OSCin. A 0.01
μ
F coupling capacitor is used for measure-
ment purposes and is the minimum size recommended for
applications. The input capacitance of the OSCin pin is
approximately 6 pF. An external feedback resistor of approxi-
mately 10 M
is required across the OSCin and OSCout pins
in the ac–coupled case. (See Figure 12.) OSCout is an inter-
nal node on the device and should not be used to drive any
loads(i.e., OSCout is unbuffered). However, the buffered
REFout is available to drive external loads in the HF mode.
The external signal level must be at least 1 V p–p; the mini-
mum and maximum frequencies are given in the
AC Electri-
cal Characteristics
table. These frequencies apply for R
Counter divide ratios as indicated in the table. For very small
ratios, the maximum frequency is limited to the divide ratio
times 1 MHz (Reason: the phase/frequency detectors are
limited to a maximum input frequency of 1 MHz).
If an external source is available which swings from at
least the VIL to VIH levels listed in the
DC Electrical Charac-
teristics
table, then dc coupling can be used. In the dc–
coupled case, no external feedback resistor is needed.
OSCout must be a No Connect to avoid loading an internal
node on the MC145173, as noted above. For frequencies be-
low 2 MHz, a signal level of at least VIL and VIH is needed,
and dc coupling must be used. The R counter is a static
counter and may be operated down to dc. However, wave
shaping by a CMOS buffer may be required to ensure fast
rise and fall times into the OSCin pin at these low frequen-
cies.
Each rising edge on the OSCin pin causes the R counter to
decrement by one. In the standby mode, OSCin is pulled low
by an on–chip FET.
REFout
Open–Drain Reference Frequency Output (Pin 23)
This output is the buffered output of the crystal–generated
reference frequency or externally provided reference source.
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