- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379305 > MC145173DW (MOTOROLA INC) Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter PDF資料下載
參數(shù)資料
| 型號： | MC145173DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 130 MHz, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁數(shù)： | 25/33頁 |
| 文件大?。?/td> | 277K |
| 代理商： | MC145173DW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
MC145173
25
MOTOROLA
PROGRAMMER’S GUIDE
(continued)
CONFIGURING FOR HF AND MF OPERATION
HF = HIGH FREQUENCY: 3 TO 30 MHZ
MF = MEDIUM FREQUENCY 500 kHZ TO 3 MHZ
The write–only registers retain data indefinitely as long as
power is applied to the device. Therefore, they do not need to
be re–written with the same data when tuning across the
band. These registers only need to be written if the contents
need to be changed.
Step 1: Load the C Register
The Out A, Out B, and Out C bits must be properly pro-
grammed to configure the Output A, Output B, and Output C
pins. These outputs switch a few nanoseconds after the C
Register is loaded, i.e., after ENB makes a low–to–high tran-
sition on a C Register access.
Step 2: Load the R Register
This register determines the tuning resolution of the radio
by setting the divide ratio of the R Counter. Also, the HF/VHF
bit must be cleared low for HF and MF operation.
As an example, assume that the external crystal con-
nected to pins 1 and 24 is 10.25 MHz. Also, assume that the
tuning resolution is 10 kHz. Then, the divide ratio needed is
10.25 MHz divided by 10 kHz; this is 1025 decimal. In hexa-
decimal, this is $401.
Loading the R Register is accomplished with 3 bytes.
Therefore, if all other bits are low, the serial data is $000401.
For HF and MF operation, the ACQ bit is usually set high for
a wide acquisition window. Therefore, it is more likely the
data is: $008401.
Tuning the HF or MF Band
To tune across the HF or MF band, the N Register needs to
be changed.
For example, if the first I.F. is 10.7 MHz, and 530 kHz
needs to be tuned, then the L.O. needs to be running at
10.7 MHz plus 530 kHz for high–side injection; this is
11.23 MHz. The resolution is 10 kHz. Therefore, the ratio re-
quired for the N Counter is 11.23 MHz divided by 10 kHz; this
is 1123 decimal. In hexadecimal, this is $463.
Loading the N register requires 2 bytes. Therefore, the se-
rial data is $0463.
To tune 1000 kHz, use 1170 decimal or $0492.
To tune 1710 kHz, use 1241 decimal or $04D9.
CONFIGURING FOR VHF OPERATION
VHF = VERY HIGH FREQUENCY: 30 TO 130 MHz
The write–only registers retain data indefinitely as long as
power is applied to the device. Therefore, they do not need to
be re–written with the same data when tuning across the
band. These registers only need to be written if the contents
need to be changed.
Step 1: Load the C Register
The Out A, Out B, and Out C bits must be properly pro-
grammed to configure the Output A, Output B, and Output C
pins. These outputs switch a few nanoseconds after the C
Register is loaded; i.e., after ENB makes a low–to–high tran-
sition on a C Register access.
Step 2: Load the R Register
This register determines the tuning resolution of the radio
by setting the divide ratio of the R Counter. Also, the HF/VHF
bit must be set high for VHF operation.
As an example, assume that the external crystal con-
nected to pins 1 and 24 is 10.35 MHz. Also, assume that the
tuning resolution is 50 kHz. Then, the divide ratio needed is
10.35 MHz divided by 50 kHz; this is 207 decimal. In hexade-
cimal, this is $CF.
Loading the R Register is accomplished with 3 bytes.
Therefore, if all other bits are low, the serial data is $0000CF.
For VHF operation, the ACQ bit is usually cleared low for a
narrow acquisition window.
Tuning the VHF Band
To tune across the VHF Band, the N Register needs to be
changed.
For example, if the I.F. is 10.7 MHz, and 87.5 MHz needs
to be tuned, then the L.O. needs to be running at 10.7 MHz
plus 87.5 MHz for high–side injection; this is 98.2 MHz. The
resolution is 50 kHz. Therefore, the ratio required for the N
Counter is 98.2 MHz divided by 50 kHz; this is 1964 decimal.
In hexadecimal, this is $7AC.
Loading the N Register requires 2 bytes. Therefore, the
serial data is $07AC.
To tune 98.5 MHz, use 2184 decimal or $0888.
To tune 107.9 MHz, use 2372 decimal or $0944.
READING THE A REGISTER
The A Register contains the binary representation of the
Analog–to–Digital Converter’s value plus the End of Conver-
sion bit (EOC). The EOC bit must be a 1 to indicate a valid
conversion. Also, the A Register has bits which indicate the
logic levels on the Input C and D pins.
Reading the Logic Levels on the Input C and D Pins
Step 1: Store the Values in the Shift Register
To store the value, set the Read A bit in the C Register to a
1. The digital value present at the Input C and D pins during
the falling edge of ENB on the read cycle is stored in the shift
register.
Step 2: Read the Serial Data
To read the Input C value only, take the ENB pin low and
shift out 8 bits. The Input C value is contained in the In C bit.
To read both the Input C and D values, take the ENB pin
low and shift out 9 or 16 bits. The values are in the In C and
In D bits.
NOTE: In D may also be read from the F Register.
Reading the Analog–to–Digital Converter Value
Step 1: Initialize
To initialize the converter, clear the I SMPL bit in the C
Register to a 0. At this time, the Read A bit in the C Register
must be 0. The Chan bit must be 0 to select Input A or 1 to
select Input B. The state may not be changed simultaneously
with the I SMPL bit being set high.
相關PDF資料 |
PDF描述 |
|---|---|
| MC145173 | Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter |
| MC145202DT | Low-Voltage 2.0 GHz PLL Frequency Synthesizer |
| MC145202EVK | Evaluation Board Manual |
| MC145202F | Low-Voltage 2.0 GHz PLL Frequency Synthesizer |
| MC14522BCL | Non-inverting Fast Synchronous Buck MOSFET Drivers with Enable 14-HTSSOP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC14517BCP | 功能描述:計數(shù)器移位寄存器 3-18V Dual 64-Bit RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14517BCPG | 功能描述:計數(shù)器移位寄存器 3-18V Dual 64-Bit Static Shift RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14517BDW | 功能描述:計數(shù)器移位寄存器 3-18V Dual 64-Bit RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14517BDWG | 功能描述:計數(shù)器移位寄存器 3-18V Dual 64-Bit Static Shift RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC14517BDWR2 | 功能描述:計數(shù)器移位寄存器 3-18V Dual 64-Bit RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。