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參數(shù)資料
| 型號： | MC145173DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 130 MHz, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 277K |
| 代理商： | MC145173DW |
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MC145173
14
MOTOROLA
R REGISTER BITS
Do not attempt to write to the R register when both the F
counter and A/D converter are simultaneously active.
POL
Polarity (R23)
The polarity bit controls both phase/frequency detector
outputs. When low, the detector outputs are per Figure 16.
When R23 is high, the output polarity of both phase/frequen-
cy detectors is inverted.
Upon power up, this bit is forced low.
RST
Reset (R22)
When high, this bit resets the device except for the serial
port. RST is kept low for normal operation. However, if a
power glitch occurs which does not reduce the power supply
voltage to 0 volts, the R register should be written twice with
the RST bit set high. Also, if the CLK pin is floating upon pow-
er up, the RST bit should be written high twice for initializa-
tion.
NOTE
The on–chip POR (power–on reset) circuit resets
the device during a cold start, if the CLK pin is not
floating or toggled during supply ramp up to 4.5 V.
This bit is automatically cleared low after the chip is reset.
HF/VHF
HF/VHF Band Selection (R21)
When this bit is low, the HFin and HF IFin inputs are en-
abled, along with the HF PDout pin. The VHF PDout pin is
forced to the float condition and VHFin is pulled low with an
on–chip FET.
When this bit is high, the VHFin and VHF IFin inputs are
enabled, along with the VHF PDout pin. Both the HF PDout
and HFin pins are forced to the high–impedance state, and
REFout is disabled (high–impedance).
K
HF IFin Response (R20)
This bit is used to control the input response of the HF IFin
pin.
When the K bit is high, the Kuligowski acceptor circuit is
engaged, which allows acceptance of signals only below the
frequency at the OSCin pin divided by 8. Use of this digital
integrator allows further suppression of high–frequency sig-
nals into the HF IFin pin.
In the VHF mode, the K bit should be kept low.
STBY
Standby (R19)
If STBY is low, the chip is in the normal mode of operation.
When this bit is high, the device is placed in the standby
state for reduced power consumption. In standby, both
phase/frequency detector outputs and the REFout pin are
forced to the high–impedance state, the Rx reference current
is shut off, and the oscillator is stopped (via an on–chip FET
pulling the OSCin pin low). The HFin, VHFin, HF IFin, and
VHF IFin inputs are shut off, which inhibits the counters from
toggling. Finally, the comparator and ADC are turned off.
Data is retained in the C, N, and R registers during standby.
CAUTION
Setting the STBY bit high aborts any frequency
count or A/D conversion which may be in
progress.
STBY is forced high upon power up.
φ
det1,
φ
det0
Phase/Frequency Detector Response (R18, R17)
Controls the VHF phase/frequency detector response per
Table 3. The HF phase/frequency detector is unaffected.
These bits also control several test modes as shown in
Table 4.
Out D
Output D Control (R16)
When cleared low, the Output D pin is forced low. When
high, Output D is high.
This bit is cleared low upon power up.
ACQ
Acquisition Window (R15)
This bit determines the frequency counter (F counter)
acquisition window. A low level is for a narrow window, and a
high is for a wide window.
The formula to determine the window is
t
2
(19
2a
)
f
where t is the acquisition window in seconds, a is the logic
level of the ACQ bit (0 or 1), and f is the frequency at the
OSCin pin in hertz.
F SMPL
Frequency Sample (R14)
When this bit is low, the frequency counter (F counter) is
initialized to all highs (ones).
When F SMPL is set high, the frequency counter “rolls
over” to zero, increments for one acquisition window, and
then holds the count. When the frequency counter is read via
the serial port, R14 must remain high; otherwise, the fre-
quency counter is initialized and outputs all ones.
F SMPL must not be set high if I SMPL is already high.
That is, a frequency count cannot be initiated if an A/D con-
version is in progress.
This bit is cleared low upon power up. However, this bit is
not automatically cleared low after a frequency count and
read sequence.
R13 to R0
R Counter Divide Ratio
These bits control the divide ratio of the R counter per Fig-
ure 18.
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