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參數(shù)資料
| 型號： | MC145173DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 130 MHz, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁數(shù)： | 12/33頁 |
| 文件大?。?/td> | 277K |
| 代理商： | MC145173DW |
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MC145173
12
MOTOROLA
C REGISTER BITS
I SMPL
Input Sample (C7)
When the input sample bit is cleared low, the ADC is held
in the initialized state. When I SMPL is set high, the ADC
converts the input channel selected by bit C4, and holds the
conversion value. When the ADC is read via the serial port,
I SMPL must remain high. Otherwise, the EOC bit is reset
low. The previous converison value is not lost, however.
I SMPL may be set at any time, even if the F SMPL bit in
the R register is already set. That is, an A/D conversion may
be initiated during an F count. The state of C4 may not be
changed simultaneously with C7 being set high.
I SMPL is cleared low upon power up. However, this bit is
not automatically cleared low after a conversion and read se-
quence.
READ A
Read A Register (C6)
Setting the Read A register bit high causes the ADC’s val-
ue and the states of Inputs C and D to be parallel loaded into
the serial port’s shift register. ENB is then taken low and ei-
ther 8, 9, or 16 bits are shifted from the Dout pin. If only 8 bits
are shifted, the state of Input D is not read. To read Input D,
use either a 9 or 16 bit shift. (See Figure 21.) Alternatively,
Input D may be read from the F Register.
While the Read A bit is set, writing to any register is inhib-
ited. After the read occurs (A register data shifted out), C6 is
automatically cleared low. When C6 is low, the shift register
is not parallel loaded and any of the registers of Table 1 may
be written.
Read A should not be set when Read F is set. If both Read
A and Read F are set simultaneously, a Read A Registerop-
eration is performed and the Read F Registerrequest is ig-
nored.
Read A is cleared low at power up.
RESERVED
Reserved Bit (C5)
This bit must be kept low.
CHAN
Channel Select for ADC (C4)
When the channel bit is low, Input A is selected to be con-
verted by the ADC. When the bit is high, Input B is selected.
The state of C4 may not be changed simultaneously with the
I SMPL bit being set high.
READ F
Read F Register (C3)
Setting the Read F register bit high causes the frequency
counter’s value and the state of Input D to be parallel loaded
into the serial port’s shift register. ENB is then taken low and
24 bits are shifted from the Dout pin. (See Figure 22.)
While the Read F bit is set, writing to any register is inhib-
ited. After the read occurs (F register data shifted out), C3 is
automatically cleared low. When C3 is low, the shift register
is not parallel loaded and any of the registers of Table 1 may
be written.
Read F should not be set when Read A is set. If both Read
F and Read A are set simultaneously, a Read A Registerop-
eration is performed and the Read F Registerrequest is ig-
nored.
Read F is cleared low at power up.
OUT C, OUT B, OUT A
Output C, Output B, Output A Control (C2, C1, C0)
When Out A, Out B, or Out C is cleared low, the Output A,
Output B, or Output C pins are forced low, respectively.
When set high, the associated output is forced high, except
for Output A which is forced to the high–impedance state.
These bits are cleared low at power up.
ENB
CLK
Din
MSB
LSB
C7
C6
C5
C4
C3
C2
C1
C0
1
2
3
4
5
6
7
8
Figure 17. C Register Access and Format (8 Clock Cycles are Used)
I SMPL
READ A
RESERVED
READ F
CHAN
OUT C
OUT A
OUT B
NOTE: This is a write–only register.
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