參數(shù)資料
型號(hào)： MC145173DW
廠商： MOTOROLA INC
元件分類： XO, clock
英文描述： Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter
中文描述： PLL FREQUENCY SYNTHESIZER, 130 MHz, PDSO24
封裝： SOG-24
文件頁(yè)數(shù)： 11/33頁(yè)
文件大?。?/td> 277K
代理商： MC145173DW
MC145173
11
MOTOROLA
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
This output is enabled and disabled via the HF/VHF bit in
the R register. VHF PDout is forced to the floating state when
disabled.
If not used, this pin should be a no connect.
Rx
External Resistor (Pin 20)
A resistor is tied between this pin and VSS. This sets a ref-
erence current which determines the current delivered
(IPDout) at the current source/sink phase/frequency detector
output, VHF PDout. For a nominal current of 2.2 mA at the
VHF PDout pin, a 15 k
resistor is utilized.
In addition, the Rx pin must be bypassed to VDD with a
low–inductance 0.1
μ
F capacitor mounted very close to
these pins. Lead lengths on the capacitor should be mini-
mized.
If the VHF PDout pin is not used, the Rx pin may be floated.
POWER SUPPLY
VDD
Most–Positive Supply Potential (Pin 17)
This pin may range from 4.5 to 5.5 V with respect to VSS.
For optimum performance, VDD should be bypassed to
VSS using low–inductance capacitor(s) mounted very close
to the MC145173. Lead lengths and traces to the capaci-
tor(s) should be minimized. (The very fast switching speed of
the device can cause excessive current spikes on the power
leads if they are improperly bypassed.)
Power supply ramp up time should be less than 20 ms
from 0 to 4.5 V. If the ramp up time exceeds 20 ms, the POR
circuit may not function and the outputs will be in an unknown
state. The RST bit must be used in this case.
VSS
Most–Negative Supply Potential (Pin 19)
This pin is usually ground.
fR
REFERENCE
OSCin
÷
R
fV
FEEDBACK
(fin
÷
N)
HF PDout
VH
VL
VH
VH
VL
HIGH IMPEDANCE
*
VH = High voltage level
VL = Low voltage level
*At this point, when both fR and fV are in phase, both the source and sink drivers are turned on for a short duration. For exceptions,
see Figure 19.
NOTE: HF PDout and VHF PDout are shown with the polarity bit (POL) = low; see Figure 18 for POL.
VL
VHF PDout
SOURCING CURRENT
FLOAT
*
SINKING CURRENT
Figure 16. Phase/Frequency Detectors Output Waveforms
相關(guān)PDF資料
PDF描述
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