參數(shù)資料
型號: MC145173
廠商: Motorola, Inc.
元件分類: 通用總線功能
英文描述: Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter
中文描述: 雙頻鎖相環(huán)頻率合成器ADC和頻率計數(shù)器
文件頁數(shù): 5/33頁
文件大?。?/td> 277K
代理商: MC145173
MC145173
5
MOTOROLA
AC INTERFACE CHARACTERISTICS
(VDD = 4.5 to 5.5 V, TA = – 40 to +85
°
C, CL = 50 pF, Input tr = tf = 10 ns unless otherwise indicated)
Symbol
Parameter
Figure #
Guaranteed
Limit
Unit
fclk
Serial Data Clock Frequency (Note: Refer to CLK tw below)
Maximum Propagation Delay, CLK to Dout
Maximum Propagation Delay, ENB to Output B, Output C, Output D
2
dc to 2.1
MHz
tPLH, tPHL
tPLH, tPHL
tPLZ, tPZL
tPLZ, tPHZ
tPZL, tPZH
tTLH, tTHL
2, 8
150
ns
6, 8
300
ns
Maximum Propagation Delay, ENB to Output A
7, 9
300
ns
Maximum Disable Time, Dout Active to High Impedance
Access Time, Dout High Impedance to Active
Maximum Output Transition Time, Dout
3, 9
400
ns
3, 9
0 to 200
ns
CL = 50 pF
2, 8
100
ns
CL = 200 pF
2, 8
400
ns
Cin
Cout
Maximum Input Capacitance – Din, ENB, CLK
Maximum Output Capacitance – Dout
10
pF
10
pF
TIMING REQUIREMENTS
(TA = –
40 to +
85
°
C, Input tr = tf = 10 ns unless otherwise indicated)
Symbol
Parameter
Figure #
Guaranteed
Limit
Unit
tsu, th
tsu, th, trec
tw(H)
tw
tr, tf
Minimum Setup and Hold Times, Din vs CLK
Minimum Setup, Hold, and Recovery Times, ENB vs CLK
4
100
ns
5
200
ns
Minimum Inactive–High Pulse Width, ENB
5
600
ns
Minimum Pulse Width, CLK
2
238
ns
Maximum Input Rise and Fall Times, CLK (Source Impedance
5 k
)
2
50
μ
s
AC ELECTRICAL CHARACTERISTICS
(VDD = 4.5 to 5.5 V, TA = –40 to +85
°
C)
Guaranteed Range
Symbol
Parameter
Test Condition
Figure #
Min
Max
Unit
fin
Input Frequency, HFin
Vin
210 mV p–p Sine Wave,
N Counter set to divide ratio
such that fV
1 MHz (Note 1)
Vin
2.2 V p–p Sine Wave,
N Counter same as above
10
10
(Note 4)
40
MHz
10
1
40
MHz
fin
Input Frequency, VHFin
Vin
210 mV p–p Sine Wave,
N Counter set to divide ratio
such that fV
1 MHz (Note 1)
Vin
1.0 V p–p Sine Wave,
R Counter set to divide ratio
such that fR
1 MHz (Note 3)
C1
30 pF, C2
30 pF,
Includes Stray Capacitance,
R Counter set to divide ratio
such that fR
1 MHz (Note 3)
Vin
85 mV p–p Sine Wave,
K bit cleared low or set high
11
40
(Note 4)
130
MHz
fin
Input Frequency, OSCin
Externally driven with ac–coupled signal
(Note 2)
12
2
(Note 4)
15
MHz
fXTAL
Crystal Frequency, OSCin and OSCout
(Note 2)
13
2
15
MHz
fin
Input Frequency, HF IFin
10
400
500
kHz
fin
Input Frequency, VHF IFin
Vin
85 mV p–p Sine Wave
10
8
(Note 4)
20
MHz
fout
Output Frequency, REFout
CL = 20 pF,
Vout
1.5 V p–p
14, 15
dc
10.4
MHz
NOTES:
1. fV is the output signal of the N Counter.
2. The ADC is guaranteed over an OSCin range of 9.5 to 10.4 MHz only.
3. fR is the output signal of the R Counter.
4. For operation below this frequency, use dc coupling with a signal level of at least VIL to VIH. See Pin Description.
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