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參數(shù)資料
| 型號(hào)： | MC143421FU |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI Bus Interface |
| 中文描述： | PCI BUS CONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 189K |
| 代理商： | MC143421FU |
MC143421
MOTOROLA
9
INTERNAL REGISTER DESCRIPTION
Offset
Bits
Description
00h
0
External reset, controlling pin ERESET
on the PIB
1
Reserved
2
Reserved
3
Reserved
5:4
00: PIB three–cycle operation
01: PIB five–cycle operation
1–: PIB twelve–cycle operation
6
Reserved
7
Reserved
01h
7:0
Reserved
02h
7:0
AUX pin control register. The
corresponding AUX pin is an output
when set to 1.
03h
7:0
AUX pin data register. When AUX pin is
set as an output, the output state will be
controlled by this register.
04h
7:0
Reserved
05h
7:0
Interrupt 1 mask register. Selects the
AUX input that will generate the interrupt.
06h
7:0
Reserved
07h
7:0
AUX pin status register. Reads the status
of the AUX pin.
29h
7:0
ACPI mask register. Set to 1 to select the
AUX input to be used to enable PME#
output. Enables an external event (such
as a ring) to switch on the computer.
2ah
7:0
AUX pin data polarity control register. Set
to 1 to invert the polarity of data.
2bh
0
AUX pin data select register. Bit 0 set to
1, AUX[6:7] becomes power state bit
(reference PCI config register 44h[1:0]).
C0 to FF
7:0
Peripheral Interface Bus Addressing
Access Procedures
All the internal registers are IO/MEM mapped. They can be
accessed with either I/O or memory read/write command
from the PCI bus.
For I/O access, the host needs to send the address with
bits A31 to A8 to match the data in configuration register 10h
bits 31 to 8. Also, the address bits 7 and 6 need to be set to
0.
For memory access, the address bits A31 to A12 need to
match the value in configuration register 14h bits 31 to 12
and the address bits 11 to 6 need to all be 0. The internal reg-
isters are byte addressable.
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