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參數(shù)資料
| 型號(hào)： | MC14052BCP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Analog Multiplexers / Demultiplexers |
| 中文描述： | 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 355K |
| 代理商： | MC14052BCP |
MOTOROLA CMOS LOGIC DATA
7
MC14051B MC14052B MC14053B
APPLICATIONS INFORMATION
Figure A illustrates use of the on–chip level converter de-
tailed in Figures 2, 3, and 4. The 0–to–5 V Digital Control sig-
nal is used to directly control a 9 Vp–p analog signal.
The digital control logic levels are determined by VDD and
VSS. The VDD voltage is the logic high voltage; the VSS volt-
age is logic low. For the example, VDD = + 5 V = logic high at
the control inputs; VSS = GND = 0 V = logic low.
The maximum analog signal level is determined by VDD
and VEE. The VDD voltage determines the maximum recom-
mended peak above VSS. The VEE voltage determines the
maximum swing below VSS. For the example, VDD – VSS =
5 V maximum swing above VSS; VSS – VEE = 5 V maximum
swing below VSS. The example shows a
±
4.5 V signal which
allows a 1/2 volt margin at each peak. If voltage transients
above VDD and/or below VEE are anticipated on the analog
channels, external diodes (Dx) are recommended as shown
in Figure B. These diodes should be small signal types able
to absorb the maximum anticipated current surges during
clipping.
The
absolute
maximum potential difference between VDD
and VEE is 18.0 V. Most parameters are specified up to 15 V
which is the
recommended
maximum difference between
VDD and VEE.
Balanced supplies are not required. However, VSS must
be greater than or equal to VEE. For example, VDD = + 10 V,
VSS = + 5 V, and VEE – 3 V is acceptable. See the Table
below.
Figure A. Application Example
+5 V
–5 V
VDD
VSS
VEE
9 Vp–p
ANALOG SIGNAL
0–TO–5 V DIGITAL
CONTROL SIGNALS
SWITCH
I/O
INHIBIT,
A, B, C
COMMON
O/I
9 Vp–p
ANALOG SIGNAL
+
4.5 V
–
4.5 V
GND
+5 V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
MC14051B
MC14052B
MC14053B
VDD
VDD
VEE
VEE
DX
DX
DX
DX
ANALOG
I/O
COMMON
O/I
VDD
VSS
VEE
Logic High/Logic Low
Maximum Analog Signal Range
+ 5
0
0
+ 5/0
+ 5 to 0 = 5 Vp–p
+ 5
0
– 5
+ 5/0
+ 5 to – 5 = 10 Vp–p
+ 10
+ 5
– 5
+ 10/ + 5
+ 10 to – 5 = 15 Vp–p
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