參數(shù)資料
型號(hào): MC14034B
廠商: Motorola, Inc.
英文描述: 8-Bit Universal Bus Register
中文描述: 8位通用總線注冊(cè)
文件頁數(shù): 7/9頁
文件大?。?/td> 313K
代理商: MC14034B
MOTOROLA CMOS LOGIC DATA
141
MC14034B
Figure 6. Shift Right/Shift Left with Parallel Inputs
A “High” (“Low”) on the Shift Left/Shift Right input allows serial data on the Shift Left Input (Shift Right Input) to enter the register
on the positive transition of the lock signal. A “high” on the “A” Enable Input disables the “A” parallel data lines on Reg. 1 and 2
and enables the “A” data lines on registers 3 and 4 and allows parallel data into registers 1 and 2. Other logic schemes may be
used in place of registers 3 and 4 for parallel loading.
When parallel inputs are not used, Reg. 3 and 4 and associated logic are not required.
*Shift left input must be disabled during parallel entry.
A ENABLE
SHIFT LEFT/
SHIFT RIGHT
SHIFT RIGHT
INPUT
CLOCK
A/S PARALLEL
ENTRY
REGISTER 1
MC14034B
SHIFT LEFT OUTPUT
AE
P/S
DS
A/B
A/S
CB1
B8
A1
A8
AE
P/S
DS
A/B
A/S
C
A1
A8
B1
B8
AE
P/S
SHIFT RIGHT
OUTPUT
REGISTER 2
MC14034B
SHIFT LEFT
INPUT*
A/S
COCK
AE
VDD
VDD
AE
P/S
DS
A/B
A/S
CB1
B8
REGISTER 3
MC14034B
REGISTER 4
MC14034B
A1
A8
AE
P/S
DS
A/B
A/S
CB1
B8
A1
A8
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