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參數資料
| 型號： | MC12429FNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 9/9頁 |
| 文件大?。?/td> | 131K |
| 代理商： | MC12429FNR2 |
4
MC12429
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
378
Figure 7 is the low impedance connections between VCC and
GND for the bypass capacitors. Combining good quality gener-
al purpose chip capacitors with good PCB layout techniques
will produce effective capacitor resonances at frequencies ad-
equate to supply the instantaneous switching current for the
12429 outputs. It is imperative that low inductance chip capaci-
tors are used; it is equally important that the board layout does
not introduce back all of the inductance saved by using the
leadless capacitors. Thin interconnect traces between the ca-
pacitor and the power plane should be avoided and multiple
large vias should be used to tie the capacitors to the buried
power planes. Fat interconnect and large vias will help to mini-
mize layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
Figure 7. PCB Board Layout for MC12429 (28 PLCC)
C2
1
C3
R1
Xtal
C1
R1 = 10-15
C1 = 0.01F
C2 = 22F
C3 = 0.01F
= VCC
= GND
= Via
Note the dotted lines circling the crystal oscillator connec-
tion to the device. The oscillator is a series resonant circuit and
the voltage amplitude across the crystal is relatively small. It is
imperative that no actively switching signals cross under the
crystal as crosstalk energy coupled to these lines could signifi-
cantly impact the jitter of the device. Special attention should
be paid to the layout of the crystal to ensure a stable, jitter free
interface between the crystal and the on–board oscillator. Note
the provisions for placing a resistor across the crystal oscillator
terminals as discussed in the crystal oscillator section of this
data sheet.
Although the MC12429 has several design features to mini-
mize the susceptibility to power supply noise (isolated power
and grounds and fully differential PLL) there still may be ap-
plications in which overall performance is being degraded due
to system power supply noise. The power supply filter and by-
pass schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most de-
signs.
Jitter Performance of the MC12429
The MC12429 exhibits long term and cycle–to–cycle jitter
which rivals that of SAW based oscillators. This jitter perfor-
mance comes with the added flexibility one gets with a synthe-
sizer over a fixed frequency oscillator.
Figure 8. RMS PLL Jitter versus VCO Frequency
0
5
10
15
20
25
200
250
300
350
400
N=1
N=2
N=4
VCO Frequency (MHz)
RMS
Jitter
(ps)
N=8
Figure 8 illustrates the RMS jitter performance of the
MC12429 across its specified VCO frequency range. Note that
the jitter is a function of both the output frequency as well as
the VCO frequency, however the VCO frequency shows a
much stronger dependence. The data presented has not been
compensated for trigger jitter, this fact provides a measure of
guardband to the reported data.
The typical method of measuring the jitter is to accumulate a
large number of cycles, create a histogram of the edge place-
ments and record peak–to–peak as well as standard devi-
ations of the jitter. Care must be taken that the measured edge
is the edge immediately following the trigger edge. All of the
jitter data reported on the MC12429 was collected in this man-
ner.
Figure 9 shows the jitter as a function of the output frequen-
cy. For the 12429 this information is probably of more impor-
tance. The flat line represents an RMS jitter value that corre-
sponds to an 8 sigma
±25ps peak–to–peak long term period
jitter. The graph shows that for output frequencies from 87.5 to
400MHz the jitter falls within the
±25ps peak–to–peak specifi-
cation. The general trend is that as the output frequency is
decreased the output edge jitter will increase.
Figure 9. RMS Jitter versus Output Frequency
0
5
10
15
20
25
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400
Output Frequency (MHz)
RMS
Jitter
(ps)
6.25ps Reference
The jitter data presented should provide users with enough
information to determine the effect on their overall timing bud-
get. The jitter performance meets the needs of most system
designs while adding the flexibility of frequency margining and
field upgrades. These features are not available with a fixed
frequency SAW oscillator.
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