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參數(shù)資料
| 型號： | MC100H660FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit ECL/TTL Load Reducing DRAM Driver |
| 中文描述： | ECL TO TTL TRANSLATOR, TRUE OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 114K |
| 代理商： | MC100H660FN |
MC10H660 MC100H660
MOTOROLA
MECL Data
DL122 — Rev 6
2–124
AC TEST SET–UP
CL = 100 pF
PULSE
GEN.
100 PF
50
B
50
A
450
D.U.T.
SCOPE
The MC10H/100 H660 ECL–TTL DRAM Address Driver
The MC 10H/100H660 was designed for use in high capacity,
highly interleaved DRAM memory boards, that directly interface
to a high speed, pipelined ECL bus interface, where new
operations may be initiated to the board at a 50 MHz rate ( e.g.
bipolar RISC systems).
The following briefly discusses the major design features of
the part over existing semiconductor devices traditionally
used in interfacing DRAMs in high performance system
environments.
1. ECL Translator
High performance memory systems of the past that were
interfaced to ECL buses had to rely on separate ECL
translators and DRAM drivers to interface to large DRAM
arrays, which is acceptable if the module is not highly
interleaved and the bus cycle time is comparable to the DRAM
access time. This becomes inadequate as the cycle time of the
interface becomes significantly faster than the address timing
requirements of the RAM, and as the degree of internal board
interleaving increases. These higher performance demands
require that the internal address and control signals
propagated to the DRAM drivers be implemented in ECL, thus
requiring the integration of the driver and translator functions.
Integration of the translator/drive function also reduces
access latency, as well as keeping DRAM timing parameters
from being violated, due to the excessive delays encountered
with separate parts.
2. MOS Drive Capacity
Outputs are specifically designed for driving large numbers
of DRAMs (
300 pF), which reduce the number of parts and
power requirements needed per board. Output voltage levels
are designed specifically for driving DRAM inputs. No ECL
translator parts on the market today provide the designer with
this drive capability as well as the flexibility to vary the number
of DRAMs that are driven by the part.
3. Transparent Latch
The latch is added to provide the capability for a memory
controller to propagate new addresses to different banks
without having to wait for the address timing constraints to be
satisfied from a previous memory operation. For system
implementations where this is acceptable, the user has the
capability to keep the latch open, thus having the part act as
an address translator/buffer, with minimal performance impact
due to the additional propagation delay incurred from the
internal latch. The latch is controlled within an already existing
DRAM timing signal.
4. 1:2 Output Fanout
This function is useful in that it reduces input loading from
the controller by a factor of two, thus significantly improving
board etch propagation delays from the controller to the large
number of translators, without the addition of ECL glue logic
parts to reduce the loading. In large memory boards, so many
translators are needed that this type of organization is not a
handicap.
5. Low Skew, Low Propagation Delay
Low skew of the part as well as fast propagation delay
enable faster overall DRAM operation to be attained than is
possible with existing parts.
6. Power and Package Pin Layout
The H660 is specifically designed with additional power and
ground pins to greatly improve simultaneous switching
performance over existing driver parts.
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