參數(shù)資料
型號(hào)： MB90P641APF
元件分類： 微控制器/微處理器
英文描述： 16-BIT, OTPROM, 17 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 39/94頁
文件大?。?/td> 1542K
代理商： MB90P641APF
44
MB90640A Series
9. Watchdog Timer and Timebase Timer
The watchdog timer consists of a 2-bit watchdog counter, a control register, and a watchdog reset controller.
The watchdog counter uses the carry-up signal from the 18-bit timebase timer as its clock source.
In addition to the 18-bit timer, the timebase timer contains an interval interrupt control circuit. The timebase
timer uses the main clock, regardless of the value of the MCS bit in the CKSCR register.
(1)
Register Configuration
(2)
Block Diagram
: 0000A8H
Address :
PONR STBR WRST ERST SRST
WTE
WT1
WT0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RR
R
W
Initial value
XXXXX111B
: 0000A9H
Address :
Reserved
—
TBIE
TBOF
TBR
TBC1
TBC0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
—
R/W
W
R/W
Initial value
1- - 00100B
R/W
R
W
—
X
: Readable and writable
: Read only
: Write only
: Unused
: Indeterminate
TBTC
WDTC
Watchdog timer control register
Timebase timer control register
TBTC
TBC1
TBC0
TBR
TBIE
TBOF
PONR
STBR
WRST
ERST
SRST
Selector
AND
Q
Selector
2-bit counter
CLR
Watchdog reset
activation circuit
WT1
WDTC
WT0
WTE
212
Timebase
interrupt
S
R
214
216
219
TBTRES
Timebase timer
Clock input
214 216 219
OF
Main clock
(OSC oscillator)
WDGRST
To internal reset
activation circuit
From power-on detection
From hardware standby
control circuit
RST pin
From the RST bit of the
STBYC register
Internal
data
bus
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