
2 ______________________________________________________________________________________
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Supply Voltage Range, VCC ................................-0.5V to +4.0V
Voltage Range at Output CML Pins.....................-0.5V to +4.0V
Voltage Range at Input CML Pins, RES, VCC_T,
and GND_T ............................................ -0.5V to (VCC + 0.7V)
Voltage Between Input CML Complementary Pair ........... ±3.3V
Voltage Between Output CML Complementary Pair ........ ±1.4V
Continuous Power Dissipation (TA = +70°C)
48-Pin TQFP (derate 36.2mW/°C above +70°C) ........2896mW
Operating Junction Temperature Range ......... -55°C to +150°C
Storage Temperature Range............................ -55°C to +150°C
Die Attach Temperature..................................................+400°C
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.5V, TA = 0°C to +70°C. Typical values are at VCC = +3.3V, external terminations = 50Ω ±1%, MAX3815A in
automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Supply Current
ICC
Clock present (CLKLOS = HIGH)
210
270
mA
Clock and data absent (CLKLOS = LOW)
12
Supply-Noise Tolerance
DC to 500kHz
200
mVP-P
EQUALIZER PERFORMANCE
Residual Output Jitter (Cables
Only) 0.25Gbps to 1.65Gbps
(Notes 1, 2, and 3)
1dB skin-effect loss at 825MHz
0.05
UI
24dB skin-effect loss at 825MHz
0.13
0.21
Residual Output Jitter (Cables
Only) 1.65Gbps to 2.25Gbps
(Notes 1, 2, and 3)
1dB skin-effect loss at 825MHz
0.1
UI
24dB skin-effect loss at 825MHz
0.14
0.28
CID Tolerance
20
Bits
CONTROL AND STATUS
CLKLOS Assert Level
Differential peak-to-peak at EQ input
with max 225MHz clock (see the Typical
Operating Characteristics for more
information)
50
mVP-P
CML INPUTS (CABLE SIDE)
Differential Input-Voltage Swing
VID
At cable input
800
1000
1200
mVP-P
Common-Mode Input Voltage
VCM
VCC -
0.4
VCC +
0.1
V
Input Resistance
RIN
Single-ended
45
50
55
W
CML OUTPUTS (ASIC SIDE)
Differential Output-Voltage Swing
VOD
50
W load, each side
to VCC
OUTLEVEL = HIGH
800
1000
1200
mVP-P
OUTLEVEL = LOW
500
With back termination as shown in Figure 4,
OUTLEVEL = OPEN
910
Output-Voltage High
Single-ended, OUTLEVEL = HIGH
VCC
mV
Output-Voltage Low
Single-ended, OUTLEVEL = HIGH
VCC -
600
VCC -
400
mV
Output Voltage During Clock
Absence (CLKLOS = LOW)
Single-ended
VCC -
10
VCC +
10
mV