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參數(shù)資料
| 型號： | M928-02-700.XXXX |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, CQCC36 |
| 封裝： | 9 X 9 MM, SMT-36 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 261K |
| 代理商： | M928-02-700.XXXX |
M928-02 Datasheet Rev 0.3
2 of 6
Revision 013003
Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400
M928-02
VCSO BASED CLOCK GENERATOR
Preliminar y In f o r m atio n
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number
Name
I/O
Configuration
Description
1,2,3,10,14,26
GND
Ground
Power supply ground.
4,9
OP_IN, nOP_IN
Input
Used for external loop filter. See Figure 4.
5,8
nOP_OUT, OP_OUT
Output
6, 7
nVC, VC
Input
11,19,33
VCC
Power
Power supply connection, connect to +3.3V
12,13
FOUT0, nFOUT0
Output
No internal terminator
Clock output pairs, differential LVPECL output
(622.08 MHz for the M928-02-622.0800)
15,16
FOUT1, nFOUT1
17,18
FOUT2, nFOUT2
20,21
FOUT3, nFOUT3
22,23
FOUT4, nFOUT4
24,25
FOUT5, nFOUT5
29,30
FOUT6, nFOUT6
31,32
FOUT7, nFOUT7
27
XTAL_1 / REF_IN
Input
External crystal connection. Also accepts
LVCMOS/LVTTL compatible clock source.
28
XTAL_2
Input
External crystal connection. Leave unconnected
when driving pin 27 with external clock reference.
34,35,36
DNC
Do Not Connect. Internal test pins.
Table 2: Pin Descriptions
Phase Locked Loop (PLL)
M928-02
VC
nVC
nOP_OUT
OP_OUT
OP_IN
nOP_IN
FOUT2
nFOUT2
FOUT4
nFOUT4
FOUT3
nFOUT3
FOUT6
nFOUT6
FOUT5
nFOUT5
FOUT7
nFOUT7
XTAL
OSC
FOUT0
nFOUT0
FOUT1
nFOUT1
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