參數(shù)資料
型號: M74HC238B1R
廠商: 意法半導(dǎo)體
英文描述: 3 TO 8 LINE DECODER
中文描述: 3至8線譯碼器
文件頁數(shù): 1/10頁
文件大?。?/td> 247K
代理商: M74HC238B1R
M54HC238
M74HC238
October 1993
3 TO 8 LINE DECODER
B1R
(Plastic Package)
ORDER CODES :
M54HC238F1R
M74HC238B1R
M74HC238M1R
M74HC238C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
DESCRIPTION
The M54/74HC238 is ahigh speed CMOS3 to 8 line
decoder fabricated insilicongate C
2
MOStechnology.
It has the same high speed performance of LSTTL
combined with true CMOSlowpower consumption. If
thedeviceisenabled, 3 binary selectinputs(A,Band
C)determine whichoneofoutputswillgohigh.Enable
input G1 is held ”Low” or either G2A or G2B is held
”High” decoding function isinhibited and all the8 out-
putsgolow.Three enable inputsareprovided toease
cascade connection and application of this address
decoder in memory systems.
Allinputs are equipped withprotection circuitsagainst
staticdischarge and transient excess voltage.
.
HIGH SPEED
t
PD
= 14 ns(TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS238
1/10
相關(guān)PDF資料
PDF描述
M74HC238C1R 3 TO 8 LINE DECODER
M74HC238M1R 3 TO 8 LINE DECODER
M74HC241F1R HC240: INVERTED - HC241/244 NON INVERTED OCTAL BUS BUFFER WITH 3 STATE OUTPUTS
M74HC241 HC240: INVERTED - HC241/244 NON INVERTED OCTAL BUS BUFFER WITH 3 STATE OUTPUTS
M74HC241B1R HC240: INVERTED - HC241/244 NON INVERTED OCTAL BUS BUFFER WITH 3 STATE OUTPUTS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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